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324 lines
10 KiB
324 lines
10 KiB
4 months ago
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/****************************************************************************
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****************************************************************************
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***
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*** This header was automatically generated from a Linux kernel header
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*** of the same name, to make information necessary for userspace to
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*** call into the kernel available to libc. It contains only constants,
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*** structures, and macros generated from the original header, and thus,
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*** contains no copyrightable information.
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***
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*** To edit the content of this header, modify the corresponding
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*** source file (e.g. under external/kernel-headers/original/) then
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*** run bionic/libc/kernel/tools/update_all.py
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***
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*** Any manual change here will be lost the next time this script will
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*** be run. You've been warned!
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***
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****************************************************************************
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****************************************************************************/
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#ifndef _UAPI__SOUND_EMU10K1_H
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#define _UAPI__SOUND_EMU10K1_H
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#ifdef __linux__
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#include <linux/types.h>
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#endif
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#define EMU10K1_CARD_CREATIVE 0x00000000
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#define EMU10K1_CARD_EMUAPS 0x00000001
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#define EMU10K1_FX8010_PCM_COUNT 8
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#define __EMU10K1_DECLARE_BITMAP(name,bits) unsigned long name[(bits) / (sizeof(unsigned long) * 8)]
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#define iMAC0 0x00
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#define iMAC1 0x01
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#define iMAC2 0x02
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#define iMAC3 0x03
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#define iMACINT0 0x04
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#define iMACINT1 0x05
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#define iACC3 0x06
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#define iMACMV 0x07
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#define iANDXOR 0x08
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#define iTSTNEG 0x09
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#define iLIMITGE 0x0a
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#define iLIMITLT 0x0b
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#define iLOG 0x0c
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#define iEXP 0x0d
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#define iINTERP 0x0e
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#define iSKIP 0x0f
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#define FXBUS(x) (0x00 + (x))
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#define EXTIN(x) (0x10 + (x))
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#define EXTOUT(x) (0x20 + (x))
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#define FXBUS2(x) (0x30 + (x))
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#define C_00000000 0x40
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#define C_00000001 0x41
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#define C_00000002 0x42
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#define C_00000003 0x43
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#define C_00000004 0x44
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#define C_00000008 0x45
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#define C_00000010 0x46
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#define C_00000020 0x47
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#define C_00000100 0x48
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#define C_00010000 0x49
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#define C_00080000 0x4a
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#define C_10000000 0x4b
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#define C_20000000 0x4c
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#define C_40000000 0x4d
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#define C_80000000 0x4e
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#define C_7fffffff 0x4f
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#define C_ffffffff 0x50
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#define C_fffffffe 0x51
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#define C_c0000000 0x52
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#define C_4f1bbcdc 0x53
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#define C_5a7ef9db 0x54
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#define C_00100000 0x55
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#define GPR_ACCU 0x56
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#define GPR_COND 0x57
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#define GPR_NOISE0 0x58
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#define GPR_NOISE1 0x59
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#define GPR_IRQ 0x5a
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#define GPR_DBAC 0x5b
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#define GPR(x) (FXGPREGBASE + (x))
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#define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x))
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#define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0x80 + (x))
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#define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x))
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#define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x))
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#define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x))
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#define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x))
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#define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x))
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#define A_ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0xc0 + (x))
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#define A_ITRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0x00 + (x))
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#define A_ETRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0xc0 + (x))
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#define A_FXBUS(x) (0x00 + (x))
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#define A_EXTIN(x) (0x40 + (x))
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#define A_P16VIN(x) (0x50 + (x))
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#define A_EXTOUT(x) (0x60 + (x))
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#define A_FXBUS2(x) (0x80 + (x))
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#define A_EMU32OUTH(x) (0xa0 + (x))
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#define A_EMU32OUTL(x) (0xb0 + (x))
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#define A3_EMU32IN(x) (0x160 + (x))
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#define A3_EMU32OUT(x) (0x1E0 + (x))
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#define A_GPR(x) (A_FXGPREGBASE + (x))
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#define CC_REG_NORMALIZED C_00000001
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#define CC_REG_BORROW C_00000002
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#define CC_REG_MINUS C_00000004
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#define CC_REG_ZERO C_00000008
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#define CC_REG_SATURATE C_00000010
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#define CC_REG_NONZERO C_00000100
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#define FXBUS_PCM_LEFT 0x00
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#define FXBUS_PCM_RIGHT 0x01
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#define FXBUS_PCM_LEFT_REAR 0x02
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#define FXBUS_PCM_RIGHT_REAR 0x03
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#define FXBUS_MIDI_LEFT 0x04
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#define FXBUS_MIDI_RIGHT 0x05
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#define FXBUS_PCM_CENTER 0x06
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#define FXBUS_PCM_LFE 0x07
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#define FXBUS_PCM_LEFT_FRONT 0x08
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#define FXBUS_PCM_RIGHT_FRONT 0x09
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#define FXBUS_MIDI_REVERB 0x0c
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#define FXBUS_MIDI_CHORUS 0x0d
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#define FXBUS_PCM_LEFT_SIDE 0x0e
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#define FXBUS_PCM_RIGHT_SIDE 0x0f
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#define FXBUS_PT_LEFT 0x14
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#define FXBUS_PT_RIGHT 0x15
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#define EXTIN_AC97_L 0x00
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#define EXTIN_AC97_R 0x01
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#define EXTIN_SPDIF_CD_L 0x02
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#define EXTIN_SPDIF_CD_R 0x03
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#define EXTIN_ZOOM_L 0x04
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#define EXTIN_ZOOM_R 0x05
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#define EXTIN_TOSLINK_L 0x06
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#define EXTIN_TOSLINK_R 0x07
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#define EXTIN_LINE1_L 0x08
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#define EXTIN_LINE1_R 0x09
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#define EXTIN_COAX_SPDIF_L 0x0a
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#define EXTIN_COAX_SPDIF_R 0x0b
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#define EXTIN_LINE2_L 0x0c
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#define EXTIN_LINE2_R 0x0d
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#define EXTOUT_AC97_L 0x00
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#define EXTOUT_AC97_R 0x01
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#define EXTOUT_TOSLINK_L 0x02
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#define EXTOUT_TOSLINK_R 0x03
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#define EXTOUT_AC97_CENTER 0x04
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#define EXTOUT_AC97_LFE 0x05
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#define EXTOUT_HEADPHONE_L 0x06
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#define EXTOUT_HEADPHONE_R 0x07
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#define EXTOUT_REAR_L 0x08
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#define EXTOUT_REAR_R 0x09
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#define EXTOUT_ADC_CAP_L 0x0a
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#define EXTOUT_ADC_CAP_R 0x0b
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#define EXTOUT_MIC_CAP 0x0c
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#define EXTOUT_AC97_REAR_L 0x0d
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#define EXTOUT_AC97_REAR_R 0x0e
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#define EXTOUT_ACENTER 0x11
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#define EXTOUT_ALFE 0x12
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#define A_EXTIN_AC97_L 0x00
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#define A_EXTIN_AC97_R 0x01
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#define A_EXTIN_SPDIF_CD_L 0x02
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#define A_EXTIN_SPDIF_CD_R 0x03
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#define A_EXTIN_OPT_SPDIF_L 0x04
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#define A_EXTIN_OPT_SPDIF_R 0x05
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#define A_EXTIN_LINE2_L 0x08
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#define A_EXTIN_LINE2_R 0x09
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#define A_EXTIN_ADC_L 0x0a
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#define A_EXTIN_ADC_R 0x0b
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#define A_EXTIN_AUX2_L 0x0c
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#define A_EXTIN_AUX2_R 0x0d
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#define A_EXTOUT_FRONT_L 0x00
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#define A_EXTOUT_FRONT_R 0x01
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#define A_EXTOUT_CENTER 0x02
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#define A_EXTOUT_LFE 0x03
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#define A_EXTOUT_HEADPHONE_L 0x04
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#define A_EXTOUT_HEADPHONE_R 0x05
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#define A_EXTOUT_REAR_L 0x06
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#define A_EXTOUT_REAR_R 0x07
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#define A_EXTOUT_AFRONT_L 0x08
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#define A_EXTOUT_AFRONT_R 0x09
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#define A_EXTOUT_ACENTER 0x0a
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#define A_EXTOUT_ALFE 0x0b
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#define A_EXTOUT_ASIDE_L 0x0c
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#define A_EXTOUT_ASIDE_R 0x0d
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#define A_EXTOUT_AREAR_L 0x0e
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#define A_EXTOUT_AREAR_R 0x0f
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#define A_EXTOUT_AC97_L 0x10
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#define A_EXTOUT_AC97_R 0x11
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#define A_EXTOUT_ADC_CAP_L 0x16
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#define A_EXTOUT_ADC_CAP_R 0x17
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#define A_EXTOUT_MIC_CAP 0x18
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#define A_C_00000000 0xc0
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#define A_C_00000001 0xc1
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#define A_C_00000002 0xc2
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#define A_C_00000003 0xc3
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#define A_C_00000004 0xc4
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#define A_C_00000008 0xc5
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#define A_C_00000010 0xc6
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#define A_C_00000020 0xc7
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#define A_C_00000100 0xc8
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#define A_C_00010000 0xc9
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#define A_C_00000800 0xca
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#define A_C_10000000 0xcb
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#define A_C_20000000 0xcc
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#define A_C_40000000 0xcd
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#define A_C_80000000 0xce
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#define A_C_7fffffff 0xcf
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#define A_C_ffffffff 0xd0
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#define A_C_fffffffe 0xd1
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#define A_C_c0000000 0xd2
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#define A_C_4f1bbcdc 0xd3
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#define A_C_5a7ef9db 0xd4
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#define A_C_00100000 0xd5
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#define A_GPR_ACCU 0xd6
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#define A_GPR_COND 0xd7
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#define A_GPR_NOISE0 0xd8
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#define A_GPR_NOISE1 0xd9
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#define A_GPR_IRQ 0xda
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#define A_GPR_DBAC 0xdb
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#define A_GPR_DBACE 0xde
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#define EMU10K1_DBG_ZC 0x80000000
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#define EMU10K1_DBG_SATURATION_OCCURED 0x02000000
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#define EMU10K1_DBG_SATURATION_ADDR 0x01ff0000
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#define EMU10K1_DBG_SINGLE_STEP 0x00008000
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#define EMU10K1_DBG_STEP 0x00004000
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#define EMU10K1_DBG_CONDITION_CODE 0x00003e00
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#define EMU10K1_DBG_SINGLE_STEP_ADDR 0x000001ff
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#define TANKMEMADDRREG_ADDR_MASK 0x000fffff
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#define TANKMEMADDRREG_CLEAR 0x00800000
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#define TANKMEMADDRREG_ALIGN 0x00400000
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#define TANKMEMADDRREG_WRITE 0x00200000
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#define TANKMEMADDRREG_READ 0x00100000
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struct snd_emu10k1_fx8010_info {
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unsigned int internal_tram_size;
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unsigned int external_tram_size;
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char fxbus_names[16][32];
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char extin_names[16][32];
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char extout_names[32][32];
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unsigned int gpr_controls;
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};
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#define EMU10K1_GPR_TRANSLATION_NONE 0
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#define EMU10K1_GPR_TRANSLATION_TABLE100 1
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#define EMU10K1_GPR_TRANSLATION_BASS 2
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#define EMU10K1_GPR_TRANSLATION_TREBLE 3
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#define EMU10K1_GPR_TRANSLATION_ONOFF 4
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enum emu10k1_ctl_elem_iface {
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EMU10K1_CTL_ELEM_IFACE_MIXER = 2,
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EMU10K1_CTL_ELEM_IFACE_PCM = 3,
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};
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struct emu10k1_ctl_elem_id {
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unsigned int pad;
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int iface;
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unsigned int device;
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unsigned int subdevice;
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unsigned char name[44];
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unsigned int index;
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};
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struct snd_emu10k1_fx8010_control_gpr {
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struct emu10k1_ctl_elem_id id;
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unsigned int vcount;
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unsigned int count;
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unsigned short gpr[32];
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unsigned int value[32];
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unsigned int min;
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unsigned int max;
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unsigned int translation;
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const unsigned int * tlv;
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};
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struct snd_emu10k1_fx8010_control_old_gpr {
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struct emu10k1_ctl_elem_id id;
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unsigned int vcount;
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unsigned int count;
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unsigned short gpr[32];
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unsigned int value[32];
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unsigned int min;
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unsigned int max;
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unsigned int translation;
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};
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struct snd_emu10k1_fx8010_code {
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char name[128];
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__EMU10K1_DECLARE_BITMAP(gpr_valid, 0x200);
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__u32 * gpr_map;
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unsigned int gpr_add_control_count;
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struct snd_emu10k1_fx8010_control_gpr * gpr_add_controls;
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unsigned int gpr_del_control_count;
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struct emu10k1_ctl_elem_id * gpr_del_controls;
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unsigned int gpr_list_control_count;
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unsigned int gpr_list_control_total;
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struct snd_emu10k1_fx8010_control_gpr * gpr_list_controls;
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__EMU10K1_DECLARE_BITMAP(tram_valid, 0x100);
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__u32 * tram_data_map;
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__u32 * tram_addr_map;
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__EMU10K1_DECLARE_BITMAP(code_valid, 1024);
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__u32 * code;
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};
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struct snd_emu10k1_fx8010_tram {
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unsigned int address;
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unsigned int size;
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unsigned int * samples;
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};
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struct snd_emu10k1_fx8010_pcm_rec {
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unsigned int substream;
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unsigned int res1;
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unsigned int channels;
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unsigned int tram_start;
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unsigned int buffer_size;
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unsigned short gpr_size;
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unsigned short gpr_ptr;
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unsigned short gpr_count;
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unsigned short gpr_tmpcount;
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unsigned short gpr_trigger;
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unsigned short gpr_running;
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||
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unsigned char pad;
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unsigned char etram[32];
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unsigned int res2;
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};
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||
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#define SNDRV_EMU10K1_VERSION SNDRV_PROTOCOL_VERSION(1, 0, 1)
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||
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#define SNDRV_EMU10K1_IOCTL_INFO _IOR('H', 0x10, struct snd_emu10k1_fx8010_info)
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||
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#define SNDRV_EMU10K1_IOCTL_CODE_POKE _IOW('H', 0x11, struct snd_emu10k1_fx8010_code)
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#define SNDRV_EMU10K1_IOCTL_CODE_PEEK _IOWR('H', 0x12, struct snd_emu10k1_fx8010_code)
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#define SNDRV_EMU10K1_IOCTL_TRAM_SETUP _IOW('H', 0x20, int)
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#define SNDRV_EMU10K1_IOCTL_TRAM_POKE _IOW('H', 0x21, struct snd_emu10k1_fx8010_tram)
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#define SNDRV_EMU10K1_IOCTL_TRAM_PEEK _IOWR('H', 0x22, struct snd_emu10k1_fx8010_tram)
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#define SNDRV_EMU10K1_IOCTL_PCM_POKE _IOW('H', 0x30, struct snd_emu10k1_fx8010_pcm_rec)
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#define SNDRV_EMU10K1_IOCTL_PCM_PEEK _IOWR('H', 0x31, struct snd_emu10k1_fx8010_pcm_rec)
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#define SNDRV_EMU10K1_IOCTL_PVERSION _IOR('H', 0x40, int)
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#define SNDRV_EMU10K1_IOCTL_STOP _IO('H', 0x80)
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#define SNDRV_EMU10K1_IOCTL_CONTINUE _IO('H', 0x81)
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#define SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER _IO('H', 0x82)
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#define SNDRV_EMU10K1_IOCTL_SINGLE_STEP _IOW('H', 0x83, int)
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#define SNDRV_EMU10K1_IOCTL_DBG_READ _IOR('H', 0x84, int)
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#endif
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