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174 lines
6.1 KiB
174 lines
6.1 KiB
4 months ago
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/****************************************************************************
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****************************************************************************
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***
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*** This header was automatically generated from a Linux kernel header
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*** of the same name, to make information necessary for userspace to
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*** call into the kernel available to libc. It contains only constants,
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*** structures, and macros generated from the original header, and thus,
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*** contains no copyrightable information.
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***
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*** To edit the content of this header, modify the corresponding
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*** source file (e.g. under external/kernel-headers/original/) then
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*** run bionic/libc/kernel/tools/update_all.py
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***
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*** Any manual change here will be lost the next time this script will
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*** be run. You've been warned!
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***
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****************************************************************************
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****************************************************************************/
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#ifndef _MSM_NPU_H_
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#define _MSM_NPU_H_
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#include <linux/types.h>
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#define MSM_NPU_IOCTL_MAGIC 'n'
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#define MSM_NPU_GET_INFO _IOWR(MSM_NPU_IOCTL_MAGIC, 1, struct msm_npu_get_info_ioctl)
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#define MSM_NPU_MAP_BUF _IOWR(MSM_NPU_IOCTL_MAGIC, 2, struct msm_npu_map_buf_ioctl)
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#define MSM_NPU_UNMAP_BUF _IOWR(MSM_NPU_IOCTL_MAGIC, 3, struct msm_npu_unmap_buf_ioctl)
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#define MSM_NPU_LOAD_NETWORK _IOWR(MSM_NPU_IOCTL_MAGIC, 4, struct msm_npu_load_network_ioctl)
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#define MSM_NPU_UNLOAD_NETWORK _IOWR(MSM_NPU_IOCTL_MAGIC, 5, struct msm_npu_unload_network_ioctl)
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#define MSM_NPU_EXEC_NETWORK _IOWR(MSM_NPU_IOCTL_MAGIC, 6, struct msm_npu_exec_network_ioctl)
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#define MSM_NPU_LOAD_NETWORK_V2 _IOWR(MSM_NPU_IOCTL_MAGIC, 7, struct msm_npu_load_network_ioctl_v2)
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#define MSM_NPU_EXEC_NETWORK_V2 _IOWR(MSM_NPU_IOCTL_MAGIC, 8, struct msm_npu_exec_network_ioctl_v2)
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#define MSM_NPU_RECEIVE_EVENT _IOR(MSM_NPU_IOCTL_MAGIC, 9, struct msm_npu_event)
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#define MSM_NPU_SET_PROP _IOW(MSM_NPU_IOCTL_MAGIC, 10, struct msm_npu_property)
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#define MSM_NPU_GET_PROP _IOW(MSM_NPU_IOCTL_MAGIC, 11, struct msm_npu_property)
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#define MSM_NPU_EVENT_TYPE_START 0x10000000
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#define MSM_NPU_EVENT_TYPE_EXEC_DONE (MSM_NPU_EVENT_TYPE_START + 1)
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#define MSM_NPU_EVENT_TYPE_EXEC_V2_DONE (MSM_NPU_EVENT_TYPE_START + 2)
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#define MSM_NPU_EVENT_TYPE_SSR (MSM_NPU_EVENT_TYPE_START + 3)
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#define MSM_NPU_MAX_INPUT_LAYER_NUM 8
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#define MSM_NPU_MAX_OUTPUT_LAYER_NUM 4
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#define MSM_NPU_MAX_PATCH_LAYER_NUM (MSM_NPU_MAX_INPUT_LAYER_NUM + MSM_NPU_MAX_OUTPUT_LAYER_NUM)
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#define MSM_NPU_PROP_ID_START 0x100
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#define MSM_NPU_PROP_ID_FW_STATE (MSM_NPU_PROP_ID_START + 0)
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#define MSM_NPU_PROP_ID_PERF_MODE (MSM_NPU_PROP_ID_START + 1)
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#define MSM_NPU_PROP_ID_PERF_MODE_MAX (MSM_NPU_PROP_ID_START + 2)
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#define MSM_NPU_PROP_ID_DRV_VERSION (MSM_NPU_PROP_ID_START + 3)
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#define MSM_NPU_PROP_ID_HARDWARE_VERSION (MSM_NPU_PROP_ID_START + 4)
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#define MSM_NPU_PROP_ID_IPC_QUEUE_INFO (MSM_NPU_PROP_ID_START + 5)
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#define MSM_NPU_PROP_ID_DRV_FEATURE (MSM_NPU_PROP_ID_START + 6)
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#define MSM_NPU_FW_PROP_ID_START 0x1000
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#define MSM_NPU_PROP_ID_DCVS_MODE (MSM_NPU_FW_PROP_ID_START + 0)
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#define MSM_NPU_PROP_ID_DCVS_MODE_MAX (MSM_NPU_FW_PROP_ID_START + 1)
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#define MSM_NPU_PROP_ID_CLK_GATING_MODE (MSM_NPU_FW_PROP_ID_START + 2)
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#define MSM_NPU_PROP_ID_HW_VERSION (MSM_NPU_FW_PROP_ID_START + 3)
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#define MSM_NPU_PROP_ID_FW_VERSION (MSM_NPU_FW_PROP_ID_START + 4)
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#define MSM_NPU_PROP_ID_FW_GETCAPS (MSM_NPU_FW_PROP_ID_START + 5)
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#define MSM_NPU_FEATURE_MULTI_EXECUTE 0x1
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#define MSM_NPU_FEATURE_ASYNC_EXECUTE 0x2
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#define PROP_PARAM_MAX_SIZE 8
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struct msm_npu_patch_info {
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uint32_t chunk_id;
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uint16_t instruction_size_in_bytes;
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uint16_t variable_size_in_bits;
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uint16_t shift_value_in_bits;
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uint32_t loc_offset;
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};
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struct msm_npu_layer {
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uint32_t layer_id;
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struct msm_npu_patch_info patch_info;
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int32_t buf_hdl;
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uint32_t buf_size;
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uint64_t buf_phys_addr;
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};
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struct msm_npu_patch_info_v2 {
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uint32_t value;
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uint32_t chunk_id;
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uint32_t instruction_size_in_bytes;
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uint32_t variable_size_in_bits;
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uint32_t shift_value_in_bits;
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uint32_t loc_offset;
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};
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struct msm_npu_patch_buf_info {
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uint64_t buf_phys_addr;
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uint32_t buf_id;
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};
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struct msm_npu_map_buf_ioctl {
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int32_t buf_ion_hdl;
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uint32_t size;
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uint64_t npu_phys_addr;
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};
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struct msm_npu_unmap_buf_ioctl {
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int32_t buf_ion_hdl;
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uint64_t npu_phys_addr;
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};
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struct msm_npu_get_info_ioctl {
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uint32_t firmware_version;
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uint32_t flags;
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};
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struct msm_npu_load_network_ioctl {
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int32_t buf_ion_hdl;
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uint64_t buf_phys_addr;
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uint32_t buf_size;
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uint32_t first_block_size;
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uint32_t flags;
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uint32_t network_hdl;
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uint32_t priority;
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uint32_t perf_mode;
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};
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struct msm_npu_load_network_ioctl_v2 {
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uint64_t buf_phys_addr;
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uint64_t patch_info;
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int32_t buf_ion_hdl;
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uint32_t buf_size;
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uint32_t first_block_size;
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uint32_t flags;
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uint32_t network_hdl;
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uint32_t priority;
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uint32_t perf_mode;
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uint32_t num_layers;
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uint32_t patch_info_num;
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uint32_t reserved;
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};
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struct msm_npu_unload_network_ioctl {
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uint32_t network_hdl;
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};
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struct msm_npu_exec_network_ioctl {
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uint32_t network_hdl;
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uint32_t input_layer_num;
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struct msm_npu_layer input_layers[MSM_NPU_MAX_INPUT_LAYER_NUM];
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uint32_t output_layer_num;
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struct msm_npu_layer output_layers[MSM_NPU_MAX_OUTPUT_LAYER_NUM];
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uint32_t patching_required;
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uint32_t async;
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uint32_t flags;
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};
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struct msm_npu_exec_network_ioctl_v2 {
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uint64_t stats_buf_addr;
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uint64_t patch_buf_info;
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uint32_t network_hdl;
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uint32_t async;
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uint32_t flags;
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uint32_t stats_buf_size;
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uint32_t patch_buf_info_num;
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uint32_t reserved;
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};
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struct msm_npu_event_execute_done {
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uint32_t network_hdl;
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int32_t exec_result;
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};
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struct msm_npu_event_execute_v2_done {
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uint32_t network_hdl;
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int32_t exec_result;
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uint32_t stats_buf_size;
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};
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struct msm_npu_event_ssr {
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uint32_t network_hdl;
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};
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struct msm_npu_event {
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uint32_t type;
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union {
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struct msm_npu_event_execute_done exec_done;
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struct msm_npu_event_execute_v2_done exec_v2_done;
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struct msm_npu_event_ssr ssr;
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uint8_t data[128];
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} u;
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uint32_t reserved[4];
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};
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struct msm_npu_property {
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uint32_t prop_id;
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uint32_t num_of_params;
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uint32_t network_hdl;
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uint32_t prop_param[PROP_PARAM_MAX_SIZE];
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};
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#endif
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