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353 lines
13 KiB
353 lines
13 KiB
4 months ago
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## This file is used by NFC NXP NCI HAL(external/libnfc-nci/halimpl/pn547)
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## and NFC Service Java Native Interface Extensions (packages/apps/Nfc/nci/jni/extns/pn547)
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###############################################################################
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# Application options
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# Logging Levels
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# NXPLOG_DEFAULT_LOGLEVEL 0x01
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# ANDROID_LOG_DEBUG 0x03
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# ANDROID_LOG_WARN 0x02
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# ANDROID_LOG_ERROR 0x01
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# ANDROID_LOG_SILENT 0x00
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NXPLOG_EXTNS_LOGLEVEL=0x01
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NXPLOG_NCIHAL_LOGLEVEL=0x01
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NXPLOG_NCIX_LOGLEVEL=0x01
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NXPLOG_NCIR_LOGLEVEL=0x01
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NXPLOG_FWDNLD_LOGLEVEL=0x01
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NXPLOG_TML_LOGLEVEL=0x01
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NFC_DEBUG_ENABLED=0x00
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###############################################################################
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# Nfc Device Node name
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NXP_NFC_DEV_NODE="/dev/nq-nci"
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###############################################################################
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# Extension for Mifare reader enable
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MIFARE_READER_ENABLE=0x01
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###############################################################################
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# Mifare Reader implementation
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# 0: General implementation
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# 1: Legacy implementation
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LEGACY_MIFARE_READER=0
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###############################################################################
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# Firmware file type
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#.so file 0x01
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#.bin file 0x02
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NXP_FW_TYPE=0x02
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###############################################################################
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# System clock source selection configuration
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#define CLK_SRC_XTAL 1
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#define CLK_SRC_PLL 2
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NXP_SYS_CLK_SRC_SEL=0x01
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###############################################################################
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# System clock frequency selection configuration
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#define CLK_FREQ_13MHZ 1
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#define CLK_FREQ_19_2MHZ 2
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#define CLK_FREQ_24MHZ 3
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#define CLK_FREQ_26MHZ 4
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#define CLK_FREQ_38_4MHZ 5
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#define CLK_FREQ_52MHZ 6
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NXP_SYS_CLK_FREQ_SEL=0x00
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###############################################################################
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# The timeout value to be used for clock request acknowledgment
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# min value = 0x01 to max = 0x06
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NXP_SYS_CLOCK_TO_CFG=0x01
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###############################################################################
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# NXP proprietary settings
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NXP_ACT_PROP_EXTN={2F, 02, 00}
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###############################################################################
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# NFC forum profile settings
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NXP_NFC_PROFILE_EXTN={20, 02, 05, 01, A0, 44, 01, 00}
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###############################################################################
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# NXP TVDD configurations settings
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# Allow NFCC to configure External TVDD, two configurations (1 and 2) supported,
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# out of them only one can be configured at a time.
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NXP_EXT_TVDD_CFG=0x02
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###############################################################################
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#config1:SLALM, 3.3V for both RM and CM
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NXP_EXT_TVDD_CFG_1={20, 02, 0F, 01, A0, 0E, 0B, 31, 01, 01, 31, 00, 00, 00, 01, 00, D0, 0C}
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###############################################################################
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#config2: use DCDC in CE, use Tx_Pwr_Req, set CFG2 mode, SLALM,
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#monitoring 5V from DCDC, 3.3V for both RM and CM, DCDCWaitTime=4.2ms
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NXP_EXT_TVDD_CFG_2={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, C2, 82, 00, BA, 1E, 14, 00, D0, 0C}
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###############################################################################
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# NXP RF configuration ALM/PLM settings
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# This section needs to be updated with the correct values based on the platform
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NXP_RF_CONF_BLK_1={
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20, 02, 19, 03,
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A0, 0D, 03, 24, 03, 80,
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A0, 0D, 06, 08, 37, 08, 76, 00, 00,
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A0, 0D, 06, 08, 42, 00, 02, F2, F2
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}
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###############################################################################
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# NXP RF configuration ALM/PLM settings
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# This section needs to be updated with the correct values based on the platform
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NXP_RF_CONF_BLK_2={
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20, 02, 10, 01, A0, AF, 0C, 83, 42, B2, 80, 00, 83, 08, B2, 80, 00, 77, 08
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}
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###############################################################################
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# NXP RF configuration ALM/PLM settings
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# This section needs to be updated with the correct values based on the platform
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NXP_RF_CONF_BLK_3={
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20, 02, 98, 01, A0, 34, 94, 23, 04, 18, 35, 00, 00, 4B, 00, 00, 71, 00, 00,
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71, 00, 00, 96, 00, 00, BC, 00, 00, BC, 00, 00, E1, 00, 00, 07, 01, 00, 07,
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01, 00, 2C, 01, 00, 2C, 01, 00, 52, 01, 00, 52, 01, 00, 77, 01, 00, 77, 01,
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00, C2, 01, 00, C2, 01, 00, 0D, 02, 00, 0D, 02, 00, 58, 02, 00, 58, 02, 00,
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EE, 02, 00, EE, 02, 00, 18, BC, 00, 00, BC, 00, 00, BC, 00, 00, BC, 00, 00,
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E1, 00, 00, E1, 00, 00, 2C, 01, 00, 2C, 01, 00, 2C, 01, 00, 2C, 01, 00, 2C,
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01, 00, DC, 05, 00, DC, 05, 00, DC, 05, 00, DC, 05, 00, DC, 05, 00, DC, 05,
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00, DC, 05, 00, DC, 05, 00, DC, 05, 00, DC, 05, 00, DC, 05, 00, DC, 05, 00,
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DC, 05, 00
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}
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###############################################################################
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# NXP RF configuration ALM/PLM settings
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# This section needs to be updated with the correct values based on the platform
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NXP_RF_CONF_BLK_4={
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20, 02, A4, 01, A0, A9, A0, 00, C1, 00, 0A, 01, 80, 41, 0A, 02, 81, 83, 0A,
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03, C0, 42, 06, 04, 80, 46, 06, 05, C3, 01, 03, 06, C2, 05, 03, 07, C2, 4A,
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03, 07, 81, 01, 01, 08, C3, 8B, 03, 08, C3, 05, 01, 09, C3, 92, 03, 09, C6,
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84, 01, 0A, C4, CC, 03, 0A, C6, 89, 01, 0B, C5, D4, 03, 0B, C7, 92, 01, 0C,
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44, 00, 03, 0C, C7, C6, 01, 0D, 42, 04, 03, 0D, C9, CE, 01, 0E, 42, 48, 03,
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0E, 03, 00, 01, 0F, 43, 50, 03, 0F, 43, 04, 01, 10, 43, 91, 03, 10, 45, 0A,
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01, 11, 44, 95, 03, 11, 46, 11, 01, 12, 46, 8E, 01, 13, 47, C5, 01, 14, 48,
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CC, 01, 15, 4B, D4, 01, 16, 4E, D7, 01, 17, 45, A2, 01, 18, 46, A6, 01, 19,
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46, AE, 01, 1A, 47, B4, 01, 1B, 48, EA, 01, 1C, 49, F0, 01
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}
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###############################################################################
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# NXP RF configuration ALM/PLM settings
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# This section needs to be updated with the correct values based on the platform
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NXP_RF_CONF_BLK_5={
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20, 02, 5B, 01, A0, 0B, 57, ED, 0D, 90, 3F, 0F, 4E, 00, 53, 95, 00, 00, 53,
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9F, 00, 00, 6B, 9F, 00, 00, 78, 9F, 00, 00, 7A, 9F, 00, 00, 86, 9F, 00, 00,
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89, 9F, 00, 00, 95, 9F, 00, 00, 9A, 9F, 00, 00, A4, 9F, 00, 00, A6, 9F, 00,
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00, B3, 9F, 00, 00, B5, 9F, 00, 00, C1, 9F, 00, 00, C4, 1F, 00, 00, D0, 1F,
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00, 00, DA, 1F, 00, 00, E1, 1F, 00, 00, EE, 1F, 00, 00, FA, 1F, 00, 00
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}
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###############################################################################
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# NXP RF configuration ALM/PLM settings
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# This section needs to be updated with the correct values based on the platform
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NXP_RF_CONF_BLK_6={
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20, 02, 18, 02,
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A0, 18, 08, 0C, 00, 54, 00, F4, FF, F9, FF,
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A0, 69, 09, 02, CF, 80, 00, 00, 07, 40, 00, 00
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}
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###############################################################################
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# Core configuration extensions
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# It includes
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# Wired mode settings A0ED, A0EE
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# Tag Detector A040, A041, A043
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# Low Power mode A007
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# Clock settings A002, A003
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# PbF settings A008
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# Clock timeout settings A004
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# eSE (SVDD) PWR REQ settings A0F2
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# Window size A0D8
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# DWP Speed A0D5
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# How eSE connected to PN553 A012
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# UICC2 bit rate A0D1
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# SWP1A interface A0D4
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# DWP intf behavior config, SVDD Load activated by default if set to 0x31 A037
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# SPI CL Sync enable A098
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NXP_CORE_CONF_EXTN={20, 02, 5B, 13,
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A0, EC, 01, 00,
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A0, ED, 01, 01,
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A0, 5E, 01, 01,
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A0, 12, 01, 02,
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A0, 40, 01, 01,
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A0, 41, 01, 02,
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A0, 43, 01, 50,
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A0, D1, 01, 02,
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A0, D4, 01, 00,
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A0, 37, 01, 35,
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A0, D8, 01, 02,
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A0, D5, 01, 0A,
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A0, 98, 01, 03,
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A0, 9C, 02, 00, 00,
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A0, AA, 04, F1, 03, 2D, 01,
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A0, 38, 04, 14, 0B, 0B, 00,
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A0, 3A, 08, 0A, 00, 0A, 00, 0A, 00, 0A, 00,
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A0, B2, 01, 19,
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A0, 91, 01, 01
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}
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###############################################################################
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# Core configuration rf field filter settings to enable set to 01 to disable set
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# to 00 last bit
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NXP_CORE_RF_FIELD={ 20, 02, 05, 01, A0, 62, 01, 00 }
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###############################################################################
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# To enable i2c fragmentation set i2c fragmentation enable 0x01 to disable set
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# to 0x00
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NXP_I2C_FRAGMENTATION_ENABLED=0x00
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###############################################################################
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# Core configuration settings
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NXP_CORE_CONF={ 20, 02, 2D, 0F,
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85, 01, 01,
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28, 01, 00,
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21, 01, 00,
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30, 01, 08,
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31, 01, 03,
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32, 01, 60,
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38, 01, 01,
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33, 00,
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54, 01, 06,
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50, 01, 02,
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5B, 01, 00,
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80, 01, 01,
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81, 01, 01,
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82, 01, 0E,
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18, 01, 01
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}
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###############################################################################
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#Enable SWP full power mode when phone is power off
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NXP_SWP_FULL_PWR_ON=0x00
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###############################################################################
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#Set the default Felica T3T System Code OffHost route Location :
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#This settings will be used when application does not set this parameter
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# host 0x00
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# eSE 0x01
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# UICC 0x02
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# UICC2 0x03
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DEFAULT_SYS_CODE_ROUTE=0xC0
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###############################################################################
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# AID Matching platform options
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# AID_MATCHING_L 0x01
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# AID_MATCHING_K 0x02
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AID_MATCHING_PLATFORM=0x01
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###############################################################################
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#CHINA_TIANJIN_RF_SETTING
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#Enable 0x01
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#Disable 0x00
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NXP_CHINA_TIANJIN_RF_ENABLED=0x01
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###############################################################################
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#SWP_SWITCH_TIMEOUT_SETTING
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# Allowed range of swp timeout setting is 0x00 to 0x3C [0 - 60].
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# Timeout in milliseconds, for example
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# No Timeout 0x00
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# 10 millisecond timeout 0x0A
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NXP_SWP_SWITCH_TIMEOUT=0x0A
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###############################################################################
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# Enable or Disable RF_STATUS_UPDATE to EseHal module
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# Disable 0x00
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# Enable 0x01
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RF_STATUS_UPDATE_ENABLE=0x00
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###############################################################################
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# Configure the single default SE to use. The default is to use the first
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# SE that is detected by the stack. This value might be used when the phone
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# supports multiple SE (e.g. 0xF3 and 0xF4) but you want to force it to use
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# one of them (e.g. 0xF4).
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DEFAULT_OFFHOST_ROUTE=0x80
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###############################################################################
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# Configure the single default SE to use. The default is to use the first
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# SE that is detected by the stack. This value might be used when the phone
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# supports multiple SE (e.g. 0xF3 and 0xF4) but you want to force it to use
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# one of them (e.g. 0xF4).
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DEFAULT_NFCF_ROUTE=0xC0
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###############################################################################
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# Configure the default NfcA/IsoDep techology and protocol route. Can be
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# either a secure element (e.g. 0xF4) or the host (0x00)
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DEFAULT_ROUTE=0x00
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###############################################################################
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# Vendor Specific Proprietary Protocol & Discovery Configuration
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# Set to 0xFF if unsupported
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# byte[0] NCI_PROTOCOL_18092_ACTIVE
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# byte[1] NCI_PROTOCOL_B_PRIME
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# byte[2] NCI_PROTOCOL_DUAL
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# byte[3] NCI_PROTOCOL_15693
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# byte[4] NCI_PROTOCOL_KOVIO
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# byte[5] NCI_PROTOCOL_MIFARE
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# byte[6] NCI_DISCOVERY_TYPE_POLL_KOVIO
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# byte[7] NCI_DISCOVERY_TYPE_POLL_B_PRIME
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# byte[8] NCI_DISCOVERY_TYPE_LISTEN_B_PRIME
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NFA_PROPRIETARY_CFG={05, FF, FF, 06, 81, 80, 70, FF, FF}
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###############################################################################
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# Bail out mode
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# If set to 1, NFCC is using bail out mode for either Type A or Type B poll.
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NFA_POLL_BAIL_OUT_MODE=0x01
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###############################################################################
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# White list of Hosts
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# This values will be the Hosts(NFCEEs) in the HCI Network.
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DEVICE_HOST_WHITE_LIST={C0, 02}
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###############################################################################
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# Extended APDU length for ISO_DEP
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ISO_DEP_MAX_TRANSCEIVE=0xFEFF
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###############################################################################
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# Choose the presence-check algorithm for type-4 tag. If not defined, the default value is 1.
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# 0 NFA_RW_PRES_CHK_DEFAULT; Let stack selects an algorithm
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# 1 NFA_RW_PRES_CHK_I_BLOCK; ISO-DEP protocol's empty I-block
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# 2 NFA_RW_PRES_CHK_ISO_DEP_NAK; Type - 4 tag protocol iso-dep nak presence check
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# command is sent waiting for rsp and ntf.
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PRESENCE_CHECK_ALGORITHM=2
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|
###############################################################################
|
||
|
|
# Configure the NFC Extras to open and use a static pipe. If the value is
|
||
|
|
# not set or set to 0, then the default is use a dynamic pipe based on a
|
||
|
|
# destination gate (see NFA_HCI_DEFAULT_DEST_GATE). Note there is a value
|
||
|
|
# for each UICC (where F3="UICC0" and F4="UICC1")
|
||
|
|
OFF_HOST_ESE_PIPE_ID=0x16
|
||
|
|
OFF_HOST_SIM_PIPE_ID=0x0A
|
||
|
|
|
||
|
|
###############################################################################
|
||
|
|
#Set the Felica T3T System Code Power state :
|
||
|
|
#This settings will be used when application does not set this parameter
|
||
|
|
# bit pos 0 = Switch On
|
||
|
|
# bit pos 1 = Switch Off
|
||
|
|
# bit pos 2 = Battery Off
|
||
|
|
# bit pos 3 = Screen On lock
|
||
|
|
# bit pos 4 = Screen off unlock
|
||
|
|
# bit pos 5 = Screen Off lock
|
||
|
|
DEFAULT_SYS_CODE_PWR_STATE=0x3B
|
||
|
|
|
||
|
|
###############################################################################
|
||
|
|
# Configure the NFCEEIDs of offhost UICC.
|
||
|
|
# UICC 0x80 (UICC)
|
||
|
|
OFFHOST_ROUTE_UICC={80}
|
||
|
|
|
||
|
|
###############################################################################
|
||
|
|
# Configure the NFCEEIDs of offhost eSEs.
|
||
|
|
# eSE 0xC0 (eSE)
|
||
|
|
OFFHOST_ROUTE_ESE={C0}
|
||
|
|
|
||
|
|
###############################################################################
|
||
|
|
# Configure the list of NFCEE for the ISO-DEP routing.
|
||
|
|
# host 0x00
|
||
|
|
# eSE 0xC0 (eSE)
|
||
|
|
# UICC 0x80 (UICC)
|
||
|
|
DEFAULT_ISODEP_ROUTE=0x80
|
||
|
|
|
||
|
|
##############################################################################
|
||
|
|
# Update Phase tirm offset signbit
|
||
|
|
NXP_PHASE_TIRM_OFFSET_SIGN_UPDATE=0x01
|
||
|
|
|