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464 lines
13 KiB
464 lines
13 KiB
4 months ago
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/*
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* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <platform_def.h>
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#include <arch.h>
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#include <asm_macros.S>
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#include <bl32/tsp/tsp.h>
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#include <lib/xlat_tables/xlat_tables_defs.h>
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#include "../tsp_private.h"
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.globl tsp_entrypoint
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.globl tsp_vector_table
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/* ---------------------------------------------
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* Populate the params in x0-x7 from the pointer
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* to the smc args structure in x0.
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* ---------------------------------------------
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*/
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.macro restore_args_call_smc
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ldp x6, x7, [x0, #TSP_ARG6]
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ldp x4, x5, [x0, #TSP_ARG4]
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ldp x2, x3, [x0, #TSP_ARG2]
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ldp x0, x1, [x0, #TSP_ARG0]
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smc #0
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.endm
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.macro save_eret_context reg1 reg2
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mrs \reg1, elr_el1
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mrs \reg2, spsr_el1
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stp \reg1, \reg2, [sp, #-0x10]!
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stp x30, x18, [sp, #-0x10]!
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.endm
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.macro restore_eret_context reg1 reg2
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ldp x30, x18, [sp], #0x10
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ldp \reg1, \reg2, [sp], #0x10
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msr elr_el1, \reg1
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msr spsr_el1, \reg2
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.endm
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func tsp_entrypoint _align=3
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#if ENABLE_PIE
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/*
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* ------------------------------------------------------------
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* If PIE is enabled fixup the Global descriptor Table only
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* once during primary core cold boot path.
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*
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* Compile time base address, required for fixup, is calculated
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* using "pie_fixup" label present within first page.
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* ------------------------------------------------------------
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*/
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pie_fixup:
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ldr x0, =pie_fixup
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and x0, x0, #~(PAGE_SIZE_MASK)
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mov_imm x1, (BL32_LIMIT - BL32_BASE)
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add x1, x1, x0
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bl fixup_gdt_reloc
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#endif /* ENABLE_PIE */
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/* ---------------------------------------------
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* Set the exception vector to something sane.
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* ---------------------------------------------
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*/
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adr x0, tsp_exceptions
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msr vbar_el1, x0
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isb
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/* ---------------------------------------------
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* Enable the SError interrupt now that the
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* exception vectors have been setup.
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* ---------------------------------------------
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*/
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msr daifclr, #DAIF_ABT_BIT
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/* ---------------------------------------------
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* Enable the instruction cache, stack pointer
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* and data access alignment checks and disable
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* speculative loads.
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* ---------------------------------------------
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*/
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mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
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mrs x0, sctlr_el1
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orr x0, x0, x1
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bic x0, x0, #SCTLR_DSSBS_BIT
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msr sctlr_el1, x0
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isb
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/* ---------------------------------------------
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* Invalidate the RW memory used by the BL32
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* image. This includes the data and NOBITS
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* sections. This is done to safeguard against
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* possible corruption of this memory by dirty
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* cache lines in a system cache as a result of
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* use by an earlier boot loader stage.
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* ---------------------------------------------
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*/
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adr x0, __RW_START__
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adr x1, __RW_END__
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sub x1, x1, x0
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bl inv_dcache_range
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/* ---------------------------------------------
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* Zero out NOBITS sections. There are 2 of them:
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* - the .bss section;
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* - the coherent memory section.
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* ---------------------------------------------
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*/
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ldr x0, =__BSS_START__
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ldr x1, =__BSS_SIZE__
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bl zeromem
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#if USE_COHERENT_MEM
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ldr x0, =__COHERENT_RAM_START__
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ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__
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bl zeromem
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#endif
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/* --------------------------------------------
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* Allocate a stack whose memory will be marked
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* as Normal-IS-WBWA when the MMU is enabled.
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* There is no risk of reading stale stack
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* memory after enabling the MMU as only the
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* primary cpu is running at the moment.
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* --------------------------------------------
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*/
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bl plat_set_my_stack
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/* ---------------------------------------------
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* Initialize the stack protector canary before
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* any C code is called.
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* ---------------------------------------------
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*/
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#if STACK_PROTECTOR_ENABLED
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bl update_stack_protector_canary
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#endif
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/* ---------------------------------------------
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* Perform TSP setup
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* ---------------------------------------------
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*/
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bl tsp_setup
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#if ENABLE_PAUTH
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/* ---------------------------------------------
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* Program APIAKey_EL1
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* and enable pointer authentication
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* ---------------------------------------------
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*/
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bl pauth_init_enable_el1
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#endif /* ENABLE_PAUTH */
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/* ---------------------------------------------
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* Jump to main function.
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* ---------------------------------------------
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*/
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bl tsp_main
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/* ---------------------------------------------
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* Tell TSPD that we are done initialising
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* ---------------------------------------------
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*/
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mov x1, x0
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mov x0, #TSP_ENTRY_DONE
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smc #0
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tsp_entrypoint_panic:
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b tsp_entrypoint_panic
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endfunc tsp_entrypoint
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/* -------------------------------------------
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* Table of entrypoint vectors provided to the
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* TSPD for the various entrypoints
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* -------------------------------------------
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*/
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vector_base tsp_vector_table
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b tsp_yield_smc_entry
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b tsp_fast_smc_entry
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b tsp_cpu_on_entry
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b tsp_cpu_off_entry
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b tsp_cpu_resume_entry
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b tsp_cpu_suspend_entry
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b tsp_sel1_intr_entry
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b tsp_system_off_entry
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b tsp_system_reset_entry
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b tsp_abort_yield_smc_entry
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/*---------------------------------------------
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* This entrypoint is used by the TSPD when this
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* cpu is to be turned off through a CPU_OFF
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* psci call to ask the TSP to perform any
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* bookeeping necessary. In the current
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* implementation, the TSPD expects the TSP to
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* re-initialise its state so nothing is done
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* here except for acknowledging the request.
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* ---------------------------------------------
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*/
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func tsp_cpu_off_entry
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bl tsp_cpu_off_main
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restore_args_call_smc
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endfunc tsp_cpu_off_entry
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/*---------------------------------------------
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* This entrypoint is used by the TSPD when the
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* system is about to be switched off (through
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* a SYSTEM_OFF psci call) to ask the TSP to
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* perform any necessary bookkeeping.
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* ---------------------------------------------
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*/
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func tsp_system_off_entry
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bl tsp_system_off_main
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restore_args_call_smc
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endfunc tsp_system_off_entry
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/*---------------------------------------------
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* This entrypoint is used by the TSPD when the
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* system is about to be reset (through a
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* SYSTEM_RESET psci call) to ask the TSP to
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* perform any necessary bookkeeping.
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* ---------------------------------------------
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*/
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func tsp_system_reset_entry
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bl tsp_system_reset_main
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restore_args_call_smc
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endfunc tsp_system_reset_entry
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/*---------------------------------------------
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* This entrypoint is used by the TSPD when this
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* cpu is turned on using a CPU_ON psci call to
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* ask the TSP to initialise itself i.e. setup
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* the mmu, stacks etc. Minimal architectural
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* state will be initialised by the TSPD when
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* this function is entered i.e. Caches and MMU
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* will be turned off, the execution state
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* will be aarch64 and exceptions masked.
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* ---------------------------------------------
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*/
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func tsp_cpu_on_entry
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/* ---------------------------------------------
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* Set the exception vector to something sane.
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* ---------------------------------------------
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*/
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adr x0, tsp_exceptions
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msr vbar_el1, x0
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isb
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/* Enable the SError interrupt */
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msr daifclr, #DAIF_ABT_BIT
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/* ---------------------------------------------
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* Enable the instruction cache, stack pointer
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* and data access alignment checks
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* ---------------------------------------------
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*/
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mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
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mrs x0, sctlr_el1
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orr x0, x0, x1
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msr sctlr_el1, x0
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isb
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/* --------------------------------------------
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* Give ourselves a stack whose memory will be
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* marked as Normal-IS-WBWA when the MMU is
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* enabled.
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* --------------------------------------------
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*/
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bl plat_set_my_stack
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/* --------------------------------------------
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* Enable MMU and D-caches together.
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* --------------------------------------------
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*/
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mov x0, #0
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bl bl32_plat_enable_mmu
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#if ENABLE_PAUTH
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/* ---------------------------------------------
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* Program APIAKey_EL1
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* and enable pointer authentication
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* ---------------------------------------------
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*/
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bl pauth_init_enable_el1
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#endif /* ENABLE_PAUTH */
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/* ---------------------------------------------
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* Enter C runtime to perform any remaining
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* book keeping
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* ---------------------------------------------
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*/
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bl tsp_cpu_on_main
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restore_args_call_smc
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/* Should never reach here */
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tsp_cpu_on_entry_panic:
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b tsp_cpu_on_entry_panic
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endfunc tsp_cpu_on_entry
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/*---------------------------------------------
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* This entrypoint is used by the TSPD when this
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* cpu is to be suspended through a CPU_SUSPEND
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* psci call to ask the TSP to perform any
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* bookeeping necessary. In the current
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* implementation, the TSPD saves and restores
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* the EL1 state.
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* ---------------------------------------------
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*/
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func tsp_cpu_suspend_entry
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bl tsp_cpu_suspend_main
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restore_args_call_smc
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endfunc tsp_cpu_suspend_entry
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/*-------------------------------------------------
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* This entrypoint is used by the TSPD to pass
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* control for `synchronously` handling a S-EL1
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* Interrupt which was triggered while executing
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* in normal world. 'x0' contains a magic number
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* which indicates this. TSPD expects control to
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* be handed back at the end of interrupt
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* processing. This is done through an SMC.
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* The handover agreement is:
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*
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* 1. PSTATE.DAIF are set upon entry. 'x1' has
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* the ELR_EL3 from the non-secure state.
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* 2. TSP has to preserve the callee saved
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* general purpose registers, SP_EL1/EL0 and
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* LR.
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* 3. TSP has to preserve the system and vfp
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* registers (if applicable).
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* 4. TSP can use 'x0-x18' to enable its C
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* runtime.
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* 5. TSP returns to TSPD using an SMC with
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* 'x0' = TSP_HANDLED_S_EL1_INTR
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* ------------------------------------------------
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*/
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func tsp_sel1_intr_entry
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#if DEBUG
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mov_imm x2, TSP_HANDLE_SEL1_INTR_AND_RETURN
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cmp x0, x2
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b.ne tsp_sel1_int_entry_panic
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#endif
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/*-------------------------------------------------
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* Save any previous context needed to perform
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* an exception return from S-EL1 e.g. context
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* from a previous Non secure Interrupt.
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* Update statistics and handle the S-EL1
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* interrupt before returning to the TSPD.
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* IRQ/FIQs are not enabled since that will
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* complicate the implementation. Execution
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* will be transferred back to the normal world
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* in any case. The handler can return 0
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* if the interrupt was handled or TSP_PREEMPTED
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* if the expected interrupt was preempted
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* by an interrupt that should be handled in EL3
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* e.g. Group 0 interrupt in GICv3. In both
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* the cases switch to EL3 using SMC with id
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* TSP_HANDLED_S_EL1_INTR. Any other return value
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* from the handler will result in panic.
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* ------------------------------------------------
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*/
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save_eret_context x2 x3
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bl tsp_update_sync_sel1_intr_stats
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bl tsp_common_int_handler
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/* Check if the S-EL1 interrupt has been handled */
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cbnz x0, tsp_sel1_intr_check_preemption
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b tsp_sel1_intr_return
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tsp_sel1_intr_check_preemption:
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/* Check if the S-EL1 interrupt has been preempted */
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mov_imm x1, TSP_PREEMPTED
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cmp x0, x1
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b.ne tsp_sel1_int_entry_panic
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tsp_sel1_intr_return:
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mov_imm x0, TSP_HANDLED_S_EL1_INTR
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restore_eret_context x2 x3
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smc #0
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/* Should never reach here */
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tsp_sel1_int_entry_panic:
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no_ret plat_panic_handler
|
||
|
|
endfunc tsp_sel1_intr_entry
|
||
|
|
|
||
|
|
/*---------------------------------------------
|
||
|
|
* This entrypoint is used by the TSPD when this
|
||
|
|
* cpu resumes execution after an earlier
|
||
|
|
* CPU_SUSPEND psci call to ask the TSP to
|
||
|
|
* restore its saved context. In the current
|
||
|
|
* implementation, the TSPD saves and restores
|
||
|
|
* EL1 state so nothing is done here apart from
|
||
|
|
* acknowledging the request.
|
||
|
|
* ---------------------------------------------
|
||
|
|
*/
|
||
|
|
func tsp_cpu_resume_entry
|
||
|
|
bl tsp_cpu_resume_main
|
||
|
|
restore_args_call_smc
|
||
|
|
|
||
|
|
/* Should never reach here */
|
||
|
|
no_ret plat_panic_handler
|
||
|
|
endfunc tsp_cpu_resume_entry
|
||
|
|
|
||
|
|
/*---------------------------------------------
|
||
|
|
* This entrypoint is used by the TSPD to ask
|
||
|
|
* the TSP to service a fast smc request.
|
||
|
|
* ---------------------------------------------
|
||
|
|
*/
|
||
|
|
func tsp_fast_smc_entry
|
||
|
|
bl tsp_smc_handler
|
||
|
|
restore_args_call_smc
|
||
|
|
|
||
|
|
/* Should never reach here */
|
||
|
|
no_ret plat_panic_handler
|
||
|
|
endfunc tsp_fast_smc_entry
|
||
|
|
|
||
|
|
/*---------------------------------------------
|
||
|
|
* This entrypoint is used by the TSPD to ask
|
||
|
|
* the TSP to service a Yielding SMC request.
|
||
|
|
* We will enable preemption during execution
|
||
|
|
* of tsp_smc_handler.
|
||
|
|
* ---------------------------------------------
|
||
|
|
*/
|
||
|
|
func tsp_yield_smc_entry
|
||
|
|
msr daifclr, #DAIF_FIQ_BIT | DAIF_IRQ_BIT
|
||
|
|
bl tsp_smc_handler
|
||
|
|
msr daifset, #DAIF_FIQ_BIT | DAIF_IRQ_BIT
|
||
|
|
restore_args_call_smc
|
||
|
|
|
||
|
|
/* Should never reach here */
|
||
|
|
no_ret plat_panic_handler
|
||
|
|
endfunc tsp_yield_smc_entry
|
||
|
|
|
||
|
|
/*---------------------------------------------------------------------
|
||
|
|
* This entrypoint is used by the TSPD to abort a pre-empted Yielding
|
||
|
|
* SMC. It could be on behalf of non-secure world or because a CPU
|
||
|
|
* suspend/CPU off request needs to abort the preempted SMC.
|
||
|
|
* --------------------------------------------------------------------
|
||
|
|
*/
|
||
|
|
func tsp_abort_yield_smc_entry
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Exceptions masking is already done by the TSPD when entering this
|
||
|
|
* hook so there is no need to do it here.
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* Reset the stack used by the pre-empted SMC */
|
||
|
|
bl plat_set_my_stack
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Allow some cleanup such as releasing locks.
|
||
|
|
*/
|
||
|
|
bl tsp_abort_smc_handler
|
||
|
|
|
||
|
|
restore_args_call_smc
|
||
|
|
|
||
|
|
/* Should never reach here */
|
||
|
|
bl plat_panic_handler
|
||
|
|
endfunc tsp_abort_yield_smc_entry
|