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90 lines
2.8 KiB
90 lines
2.8 KiB
4 months ago
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/*
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* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef TZC_COMMON_H
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#define TZC_COMMON_H
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#include <lib/utils_def.h>
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/*
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* Offset of core registers from the start of the base of configuration
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* registers for each region.
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*/
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/* ID Registers */
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#define PID0_OFF U(0xfe0)
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#define PID1_OFF U(0xfe4)
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#define PID2_OFF U(0xfe8)
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#define PID3_OFF U(0xfec)
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#define PID4_OFF U(0xfd0)
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#define CID0_OFF U(0xff0)
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#define CID1_OFF U(0xff4)
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#define CID2_OFF U(0xff8)
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#define CID3_OFF U(0xffc)
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/*
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* What type of action is expected when an access violation occurs.
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* The memory requested is returned as zero. But we can also raise an event to
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* let the system know it happened.
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* We can raise an interrupt(INT) and/or cause an exception(ERR).
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* TZC_ACTION_NONE - No interrupt, no Exception
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* TZC_ACTION_ERR - No interrupt, raise exception -> sync external
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* data abort
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* TZC_ACTION_INT - Raise interrupt, no exception
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* TZC_ACTION_ERR_INT - Raise interrupt, raise exception -> sync
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* external data abort
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*/
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#define TZC_ACTION_NONE U(0)
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#define TZC_ACTION_ERR U(1)
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#define TZC_ACTION_INT U(2)
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#define TZC_ACTION_ERR_INT (TZC_ACTION_ERR | TZC_ACTION_INT)
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/* Bit positions of TZC_ACTION registers */
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#define TZC_ACTION_RV_SHIFT 0
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#define TZC_ACTION_RV_MASK U(0x3)
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#define TZC_ACTION_RV_LOWOK U(0x0)
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#define TZC_ACTION_RV_LOWERR U(0x1)
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#define TZC_ACTION_RV_HIGHOK U(0x2)
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#define TZC_ACTION_RV_HIGHERR U(0x3)
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/*
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* Controls secure access to a region. If not enabled secure access is not
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* allowed to region.
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*/
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#define TZC_REGION_S_NONE U(0)
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#define TZC_REGION_S_RD U(1)
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#define TZC_REGION_S_WR U(2)
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#define TZC_REGION_S_RDWR (TZC_REGION_S_RD | TZC_REGION_S_WR)
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#define TZC_REGION_ATTR_S_RD_SHIFT 30
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#define TZC_REGION_ATTR_S_WR_SHIFT 31
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#define TZC_REGION_ATTR_F_EN_SHIFT 0
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#define TZC_REGION_ATTR_SEC_SHIFT 30
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#define TZC_REGION_ATTR_S_RD_MASK U(0x1)
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#define TZC_REGION_ATTR_S_WR_MASK U(0x1)
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#define TZC_REGION_ATTR_SEC_MASK U(0x3)
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#define TZC_REGION_ACCESS_WR_EN_SHIFT 16
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#define TZC_REGION_ACCESS_RD_EN_SHIFT 0
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#define TZC_REGION_ACCESS_ID_MASK U(0xf)
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/* Macros for allowing Non-Secure access to a region based on NSAID */
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#define TZC_REGION_ACCESS_RD(nsaid) \
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((U(1) << ((nsaid) & TZC_REGION_ACCESS_ID_MASK)) << \
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TZC_REGION_ACCESS_RD_EN_SHIFT)
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#define TZC_REGION_ACCESS_WR(nsaid) \
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((U(1) << ((nsaid) & TZC_REGION_ACCESS_ID_MASK)) << \
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TZC_REGION_ACCESS_WR_EN_SHIFT)
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#define TZC_REGION_ACCESS_RDWR(nsaid) \
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(TZC_REGION_ACCESS_RD(nsaid) | \
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TZC_REGION_ACCESS_WR(nsaid))
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/* Returns offset of registers to program for a given region no */
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#define TZC_REGION_OFFSET(region_size, region_no) \
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((region_size) * (region_no))
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#endif /* TZC_COMMON_H */
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