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54 lines
1.4 KiB
54 lines
1.4 KiB
4 months ago
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef HIKEY960_DEF_H
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#define HIKEY960_DEF_H
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#include <common/tbbr/tbbr_img_def.h>
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#include <plat/common/common_def.h>
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#define DDR_BASE 0x0
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#define DDR_SIZE 0xE0000000
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#define DEVICE_BASE 0xE0000000
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#define DEVICE_SIZE 0x20000000
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/* Memory location options for TSP */
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#define HIKEY960_SRAM_ID 0
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#define HIKEY960_DRAM_ID 1
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/*
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* DDR for OP-TEE (32MB from 0x3E00000-0x3FFFFFFF) is divided in several
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* regions:
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* - Secure DDR (default is the top 16MB) used by OP-TEE
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* - Non-secure DDR used by OP-TEE (shared memory and padding) (4MB)
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* - Secure DDR (4MB aligned on 4MB) for OP-TEE's "Secure Data Path" feature
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* - Non-secure DDR (8MB) reserved for OP-TEE's future use
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*/
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#define DDR_SEC_SIZE 0x01000000
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#define DDR_SEC_BASE 0x3F000000
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#define DDR_SDP_SIZE 0x00400000
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#define DDR_SDP_BASE (DDR_SEC_BASE - 0x400000 /* align */ - \
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DDR_SDP_SIZE)
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/*
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* PL011 related constants
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*/
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#define PL011_UART5_BASE 0xFDF05000
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#define PL011_UART6_BASE 0xFFF32000
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#define PL011_BAUDRATE 115200
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#define PL011_UART_CLK_IN_HZ 19200000
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#define UFS_BASE 0
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#define HIKEY960_UFS_DESC_BASE 0x20000000
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#define HIKEY960_UFS_DESC_SIZE 0x00200000 /* 2MB */
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#define HIKEY960_UFS_DATA_BASE 0x10000000
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#define HIKEY960_UFS_DATA_SIZE 0x0A000000 /* 160MB */
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#endif /* HIKEY960_DEF_H */
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