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117 lines
2.8 KiB
117 lines
2.8 KiB
4 months ago
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/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <string.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <common/tbbr/tbbr_img_def.h>
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#include <drivers/arm/pl011.h>
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#include <drivers/arm/pl061_gpio.h>
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#include <drivers/generic_delay_timer.h>
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#include <drivers/mmc.h>
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#include <drivers/synopsys/dw_mmc.h>
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#include <lib/mmio.h>
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#include <plat/common/platform.h>
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#include "hi3798cv200.h"
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#include "plat_private.h"
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/* Data structure which holds the extents of the trusted RAM for BL1 */
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static meminfo_t bl1_tzram_layout;
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static meminfo_t bl2_tzram_layout;
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static console_t console;
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/*
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* Cannot use default weak implementation in bl1_main.c because BL1 RW data is
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* not at the top of the secure memory.
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*/
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int bl1_plat_handle_post_image_load(unsigned int image_id)
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{
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image_desc_t *image_desc;
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entry_point_info_t *ep_info;
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if (image_id != BL2_IMAGE_ID)
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return 0;
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/* Get the image descriptor */
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image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
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assert(image_desc != NULL);
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/* Get the entry point info */
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ep_info = &image_desc->ep_info;
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bl2_tzram_layout.total_base = BL2_BASE;
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bl2_tzram_layout.total_size = BL32_LIMIT - BL2_BASE;
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flush_dcache_range((uintptr_t)&bl2_tzram_layout, sizeof(meminfo_t));
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ep_info->args.arg1 = (uintptr_t)&bl2_tzram_layout;
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VERBOSE("BL1: BL2 memory layout address = %p\n",
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(void *)&bl2_tzram_layout);
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return 0;
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}
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void bl1_early_platform_setup(void)
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{
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/* Initialize the console to provide early debug support */
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console_pl011_register(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ,
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PL011_BAUDRATE, &console);
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/* Allow BL1 to see the whole Trusted RAM */
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bl1_tzram_layout.total_base = BL1_RW_BASE;
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bl1_tzram_layout.total_size = BL1_RW_SIZE;
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INFO("BL1: 0x%lx - 0x%lx [size = %zu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT,
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BL1_RAM_LIMIT - BL1_RAM_BASE);
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}
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void bl1_plat_arch_setup(void)
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{
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plat_configure_mmu_el3(bl1_tzram_layout.total_base,
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bl1_tzram_layout.total_size,
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BL1_RO_BASE, /* l-loader and BL1 ROM */
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BL1_RO_LIMIT,
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BL_COHERENT_RAM_BASE,
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BL_COHERENT_RAM_END);
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}
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void bl1_platform_setup(void)
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{
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int i;
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#if !POPLAR_RECOVERY
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struct mmc_device_info info;
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dw_mmc_params_t params = EMMC_INIT_PARAMS(POPLAR_EMMC_DESC_BASE);
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#endif
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generic_delay_timer_init();
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pl061_gpio_init();
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for (i = 0; i < GPIO_MAX; i++)
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pl061_gpio_register(GPIO_BASE(i), i);
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#if !POPLAR_RECOVERY
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/* SoC-specific emmc register are initialized/configured by bootrom */
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INFO("BL1: initializing emmc\n");
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info.mmc_dev_type = MMC_IS_EMMC;
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dw_mmc_init(¶ms, &info);
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#endif
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plat_io_setup();
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}
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unsigned int bl1_plat_get_next_image_id(void)
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{
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return BL2_IMAGE_ID;
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}
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