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95 lines
2.9 KiB
95 lines
2.9 KiB
4 months ago
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/*
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* Copyright 2019-2020 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <lib/psci/psci.h>
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#include <lib/smccc.h>
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#include <services/std_svc.h>
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#include <gpc.h>
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#include <imx_sip_svc.h>
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#include <platform_def.h>
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#define CCGR(x) (0x4000 + (x) * 0x10)
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void imx_gpc_init(void)
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{
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unsigned int val;
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int i;
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/* mask all the wakeup irq by default */
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for (i = 0; i < 4; i++) {
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mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_A53 + i * 4, ~0x0);
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mmio_write_32(IMX_GPC_BASE + IMR1_CORE1_A53 + i * 4, ~0x0);
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mmio_write_32(IMX_GPC_BASE + IMR1_CORE2_A53 + i * 4, ~0x0);
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mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53 + i * 4, ~0x0);
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mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_M4 + i * 4, ~0x0);
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}
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val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC);
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/* use GIC wake_request to wakeup C0~C3 from LPM */
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val |= CORE_WKUP_FROM_GIC;
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/* clear the MASTER0 LPM handshake */
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val &= ~MASTER0_LPM_HSK;
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mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val);
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/* clear MASTER1 & MASTER2 mapping in CPU0(A53) */
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mmio_clrbits_32(IMX_GPC_BASE + MST_CPU_MAPPING, (MASTER1_MAPPING |
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MASTER2_MAPPING));
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/* set all mix/PU in A53 domain */
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mmio_write_32(IMX_GPC_BASE + PGC_CPU_0_1_MAPPING, 0xffff);
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/*
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* Set the CORE & SCU power up timing:
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* SW = 0x1, SW2ISO = 0x1;
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* the CPU CORE and SCU power up timming counter
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* is drived by 32K OSC, each domain's power up
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* latency is (SW + SW2ISO) / 32768
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*/
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mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(0) + 0x4, 0x401);
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mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(1) + 0x4, 0x401);
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mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(2) + 0x4, 0x401);
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mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(3) + 0x4, 0x401);
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mmio_write_32(IMX_GPC_BASE + PLAT_PGC_PCR + 0x4, 0x401);
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mmio_write_32(IMX_GPC_BASE + PGC_SCU_TIMING,
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(0x59 << TMC_TMR_SHIFT) | 0x5B | (0x2 << TRC1_TMC_SHIFT));
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/* set DUMMY PDN/PUP ACK by default for A53 domain */
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mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53,
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A53_DUMMY_PUP_ACK | A53_DUMMY_PDN_ACK);
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/* clear DSM by default */
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val = mmio_read_32(IMX_GPC_BASE + SLPCR);
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val &= ~SLPCR_EN_DSM;
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/* enable the fast wakeup wait mode */
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val |= SLPCR_A53_FASTWUP_WAIT_MODE;
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/* clear the RBC */
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val &= ~(0x3f << SLPCR_RBC_COUNT_SHIFT);
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/* set the STBY_COUNT to 0x5, (128 * 30)us */
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val &= ~(0x7 << SLPCR_STBY_COUNT_SHFT);
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val |= (0x5 << SLPCR_STBY_COUNT_SHFT);
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mmio_write_32(IMX_GPC_BASE + SLPCR, val);
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/*
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* USB PHY power up needs to make sure RESET bit in SRC is clear,
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* otherwise, the PU power up bit in GPC will NOT self-cleared.
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* only need to do it once.
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*/
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mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1);
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/* enable all the power domain by default */
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for (i = 0; i < 103; i++)
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mmio_write_32(IMX_CCM_BASE + CCGR(i), 0x3);
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mmio_write_32(IMX_GPC_BASE + PU_PGC_UP_TRG, 0x485);
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}
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