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140 lines
3.6 KiB
140 lines
3.6 KiB
4 months ago
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/*
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* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <platform_def.h>
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.globl plat_my_core_pos
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.globl plat_get_my_entrypoint
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.globl platform_mem_init
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.globl plat_qemu_calc_core_pos
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.globl plat_crash_console_init
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.globl plat_crash_console_putc
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.globl plat_crash_console_flush
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.globl plat_secondary_cold_boot_setup
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.globl plat_get_my_entrypoint
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.globl plat_is_my_cpu_primary
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func plat_my_core_pos
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ldcopr r0, MPIDR
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b plat_qemu_calc_core_pos
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endfunc plat_my_core_pos
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/*
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* unsigned int plat_qemu_calc_core_pos(u_register_t mpidr);
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* With this function: CorePos = (ClusterId * 4) + CoreId
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*/
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func plat_qemu_calc_core_pos
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and r1, r0, #MPIDR_CPU_MASK
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and r0, r0, #MPIDR_CLUSTER_MASK
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add r0, r1, r0, LSR #6
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bx lr
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endfunc plat_qemu_calc_core_pos
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/* -----------------------------------------------------
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* unsigned int plat_is_my_cpu_primary (void);
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*
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* Find out whether the current cpu is the primary
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* cpu.
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* -----------------------------------------------------
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*/
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func plat_is_my_cpu_primary
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ldcopr r0, MPIDR
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ldr r1, =(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
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and r0, r1
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cmp r0, #QEMU_PRIMARY_CPU
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moveq r0, #1
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movne r0, #0
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bx lr
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endfunc plat_is_my_cpu_primary
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/* -----------------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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*
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* This function performs any platform specific actions
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* needed for a secondary cpu after a cold reset e.g
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* mark the cpu's presence, mechanism to place it in a
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* holding pen etc.
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* -----------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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/* Calculate address of our hold entry */
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bl plat_my_core_pos
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lsl r0, r0, #PLAT_QEMU_HOLD_ENTRY_SHIFT
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mov_imm r2, PLAT_QEMU_HOLD_BASE
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/* Wait until we have a go */
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poll_mailbox:
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ldr r1, [r2, r0]
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cmp r1, #PLAT_QEMU_HOLD_STATE_WAIT
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beq 1f
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/* Clear the mailbox again ready for next time. */
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mov r1, #PLAT_QEMU_HOLD_STATE_WAIT
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str r1, [r2, r0]
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/* Jump to the provided entrypoint. */
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mov_imm r0, PLAT_QEMU_TRUSTED_MAILBOX_BASE
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ldr r1, [r0]
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bx r1
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1:
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wfe
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b poll_mailbox
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endfunc plat_secondary_cold_boot_setup
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func plat_get_my_entrypoint
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/* TODO support warm boot */
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mov r0, #0
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bx lr
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endfunc plat_get_my_entrypoint
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func platform_mem_init
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bx lr
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endfunc platform_mem_init
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/* ---------------------------------------------
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* int plat_crash_console_init(void)
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* Function to initialize the crash console
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* without a C Runtime to print crash report.
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* Clobber list : x0, x1, x2
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* ---------------------------------------------
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*/
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func plat_crash_console_init
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mov_imm r0, PLAT_QEMU_CRASH_UART_BASE
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mov_imm r1, PLAT_QEMU_CRASH_UART_CLK_IN_HZ
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mov_imm r2, PLAT_QEMU_CONSOLE_BAUDRATE
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b console_pl011_core_init
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endfunc plat_crash_console_init
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/* ---------------------------------------------
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* int plat_crash_console_putc(int c)
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* Function to print a character on the crash
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* console without a C Runtime.
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* Clobber list : x1, x2
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* ---------------------------------------------
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*/
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func plat_crash_console_putc
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mov_imm r1, PLAT_QEMU_CRASH_UART_BASE
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b console_pl011_core_putc
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endfunc plat_crash_console_putc
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/* ---------------------------------------------
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* void plat_crash_console_flush(int c)
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* Function to force a write of all buffered
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* data that hasn't been output.
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* Out : void.
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* Clobber list : x0, x1
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* ---------------------------------------------
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*/
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func plat_crash_console_flush
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mov_imm r0, PLAT_QEMU_CRASH_UART_BASE
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b console_pl011_core_flush
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endfunc plat_crash_console_flush
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