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363 lines
12 KiB
363 lines
12 KiB
4 months ago
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/*
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* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <lib/mmio.h>
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#include <lib/utils_def.h>
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#include "axi_registers.h"
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#include "lifec_registers.h"
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#include "micro_delay.h"
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static void lifec_security_setting(void);
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static void axi_security_setting(void);
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static const struct {
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uint32_t reg;
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uint32_t val;
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} lifec[] = {
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/*
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* LIFEC0 (SECURITY) settings
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* Security attribute setting for master ports
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* Bit 0: ARM realtime core (Cortex-R7) master port
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* 0: Non-Secure
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*/
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{ SEC_SRC, 0x0000001EU },
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/*
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* Security attribute setting for slave ports 0 to 15
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* {SEC_SEL0, 0xFFFFFFFFU},
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* {SEC_SEL1, 0xFFFFFFFFU},
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* {SEC_SEL2, 0xFFFFFFFFU},
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* Bit19: AXI-Bus (Main Memory domain AXI) slave ports
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* 0: registers accessed from secure resource only
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* Bit 9: DBSC4 register access slave ports.
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* 0: registers accessed from secure resource only.
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*/
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#if (LIFEC_DBSC_PROTECT_ENABLE == 1)
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{ SEC_SEL3, 0xFFF7FDFFU },
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#else /* LIFEC_DBSC_PROTECT_ENABLE == 1 */
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{ SEC_SEL3, 0xFFFFFFFFU },
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#endif /* LIFEC_DBSC_PROTECT_ENABLE == 1 */
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/*
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* {SEC_SEL4, 0xFFFFFFFFU},
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* Bit 6: Boot ROM slave ports.
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* 0: registers accessed from secure resource only
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*/
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{ SEC_SEL5, 0xFFFFFFBFU },
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/*
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* Bit13: SCEG PKA (secure APB) slave ports
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* 0: registers accessed from secure resource only
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* 1: Reserved[R-Car E3]
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* Bit12: SCEG PKA (public APB) slave ports
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* 0: registers accessed from secure resource only
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* 1: Reserved[R-Car E3]
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* Bit10: SCEG Secure Core slave ports
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* 0: registers accessed from secure resource only
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*/
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#if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3)
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{ SEC_SEL6, 0xFFFFFBFFU },
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#else /* (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3) */
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{ SEC_SEL6, 0xFFFFCBFFU },
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#endif /* (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3) */
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/*
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* {SEC_SEL7, 0xFFFFFFFFU},
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* {SEC_SEL8, 0xFFFFFFFFU},
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* {SEC_SEL9, 0xFFFFFFFFU},
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* {SEC_SEL10, 0xFFFFFFFFU},
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* {SEC_SEL11, 0xFFFFFFFFU},
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* {SEC_SEL12, 0xFFFFFFFFU},
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* Bit22: RPC slave ports.
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* 0: registers accessed from secure resource only.
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*/
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#if (RCAR_RPC_HYPERFLASH_LOCKED == 1)
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{ SEC_SEL13, 0xFFBFFFFFU },
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#endif /* (RCAR_RPC_HYPERFLASH_LOCKED == 1) */
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/*
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* Bit27: System Timer (SCMT) slave ports
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* 0: registers accessed from secure resource only
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* Bit26: System Watchdog Timer (SWDT) slave ports
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* 0: registers accessed from secure resource only
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*/
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{ SEC_SEL14, 0xF3FFFFFFU },
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/*
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* Bit13: RST slave ports.
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* 0: registers accessed from secure resource only
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* Bit 7: Life Cycle 0 slave ports
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* 0: registers accessed from secure resource only
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*/
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{ SEC_SEL15, 0xFFFFFF3FU },
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/*
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* Security group 0 attribute setting for master ports 0
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* Security group 1 attribute setting for master ports 0
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* {SEC_GRP0CR0, 0x00000000U},
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* {SEC_GRP1CR0, 0x00000000U},
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* Security group 0 attribute setting for master ports 1
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* Security group 1 attribute setting for master ports 1
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* {SEC_GRP0CR1, 0x00000000U},
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* {SEC_GRP1CR1, 0x00000000U},
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* Security group 0 attribute setting for master ports 2
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* Security group 1 attribute setting for master ports 2
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* Bit17: SCEG Secure Core master ports.
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* SecurityGroup3
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*/
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{ SEC_GRP0CR2, 0x00020000U },
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{ SEC_GRP1CR2, 0x00020000U },
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/*
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* Security group 0 attribute setting for master ports 3
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* Security group 1 attribute setting for master ports 3
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* {SEC_GRP0CR3, 0x00000000U},
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* {SEC_GRP1CR3, 0x00000000U},
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* Security group 0 attribute setting for slave ports 0
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* Security group 1 attribute setting for slave ports 0
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* {SEC_GRP0COND0, 0x00000000U},
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* {SEC_GRP1COND0, 0x00000000U},
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* Security group 0 attribute setting for slave ports 1
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* Security group 1 attribute setting for slave ports 1
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* {SEC_GRP0COND1, 0x00000000U},
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* {SEC_GRP1COND1, 0x00000000U},
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* Security group 0 attribute setting for slave ports 2
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* Security group 1 attribute setting for slave ports 2
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* {SEC_GRP0COND2, 0x00000000U},
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* {SEC_GRP1COND2, 0x00000000U},
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* Security group 0 attribute setting for slave ports 3
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* Security group 1 attribute setting for slave ports 3
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* Bit19: AXI-Bus (Main Memory domain AXI) slave ports.
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* SecurityGroup3
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* Bit 9: DBSC4 register access slave ports.
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* SecurityGroup3
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*/
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#if (LIFEC_DBSC_PROTECT_ENABLE == 1)
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{ SEC_GRP0COND3, 0x00080200U },
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{ SEC_GRP1COND3, 0x00080200U },
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#else /* (LIFEC_DBSC_PROTECT_ENABLE == 1) */
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{ SEC_GRP0COND3, 0x00000000U },
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{ SEC_GRP1COND3, 0x00000000U },
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#endif /* (LIFEC_DBSC_PROTECT_ENABLE == 1) */
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/*
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* Security group 0 attribute setting for slave ports 4
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* Security group 1 attribute setting for slave ports 4
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* {SEC_GRP0COND4, 0x00000000U},
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* {SEC_GRP1COND4, 0x00000000U},
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* Security group 0 attribute setting for slave ports 5
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* Security group 1 attribute setting for slave ports 5
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* Bit 6: Boot ROM slave ports
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* SecurityGroup3
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*/
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{ SEC_GRP0COND5, 0x00000040U },
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{ SEC_GRP1COND5, 0x00000040U },
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/*
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* Security group 0 attribute setting for slave ports 6
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* Security group 1 attribute setting for slave ports 6
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* Bit13: SCEG PKA (secure APB) slave ports
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* SecurityGroup3
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* Reserved[R-Car E3]
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* Bit12: SCEG PKA (public APB) slave ports
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* SecurityGroup3
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* Reserved[R-Car E3]
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* Bit10: SCEG Secure Core slave ports
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* SecurityGroup3
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*/
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#if RCAR_LSI == RCAR_E3
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{ SEC_GRP0COND6, 0x00000400U },
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{ SEC_GRP1COND6, 0x00000400U },
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#else /* RCAR_LSI == RCAR_E3 */
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{ SEC_GRP0COND6, 0x00003400U },
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{ SEC_GRP1COND6, 0x00003400U },
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#endif /* RCAR_LSI == RCAR_E3 */
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/*
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* Security group 0 attribute setting for slave ports 7
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* Security group 1 attribute setting for slave ports 7
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* {SEC_GRP0COND7, 0x00000000U},
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* {SEC_GRP1COND7, 0x00000000U},
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* Security group 0 attribute setting for slave ports 8
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* Security group 1 attribute setting for slave ports 8
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* {SEC_GRP0COND8, 0x00000000U},
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* {SEC_GRP1COND8, 0x00000000U},
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* Security group 0 attribute setting for slave ports 9
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* Security group 1 attribute setting for slave ports 9
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* {SEC_GRP0COND9, 0x00000000U},
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* {SEC_GRP1COND9, 0x00000000U},
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* Security group 0 attribute setting for slave ports 10
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* Security group 1 attribute setting for slave ports 10
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* {SEC_GRP0COND10, 0x00000000U},
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* {SEC_GRP1COND10, 0x00000000U},
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* Security group 0 attribute setting for slave ports 11
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* Security group 1 attribute setting for slave ports 11
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* {SEC_GRP0COND11, 0x00000000U},
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* {SEC_GRP1COND11, 0x00000000U},
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* Security group 0 attribute setting for slave ports 12
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* Security group 1 attribute setting for slave ports 12
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* {SEC_GRP0COND12, 0x00000000U},
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* {SEC_GRP1COND12, 0x00000000U},
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* Security group 0 attribute setting for slave ports 13
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* Security group 1 attribute setting for slave ports 13
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* Bit22: RPC slave ports.
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* SecurityGroup3
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*/
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#if (RCAR_RPC_HYPERFLASH_LOCKED == 1)
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{ SEC_GRP0COND13, 0x00400000U },
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{ SEC_GRP1COND13, 0x00400000U },
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#endif /* (RCAR_RPC_HYPERFLASH_LOCKED == 1) */
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/*
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* Security group 0 attribute setting for slave ports 14
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* Security group 1 attribute setting for slave ports 14
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* Bit26: System Timer (SCMT) slave ports
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* SecurityGroup3
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* Bit27: System Watchdog Timer (SWDT) slave ports
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* SecurityGroup3
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*/
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{ SEC_GRP0COND14, 0x0C000000U },
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{ SEC_GRP1COND14, 0x0C000000U },
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/*
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* Security group 0 attribute setting for slave ports 15
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* Security group 1 attribute setting for slave ports 15
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* Bit13: RST slave ports
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* SecurityGroup3
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* Bit 7: Life Cycle 0 slave ports
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* SecurityGroup3
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* Bit 6: TDBG slave ports
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* SecurityGroup3
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*/
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{ SEC_GRP0COND15, 0x000000C0U },
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{ SEC_GRP1COND15, 0x000000C0U },
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/*
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* Security write protection attribute setting slave ports 0
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* {SEC_READONLY0, 0x00000000U},
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* Security write protection attribute setting slave ports 1
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* {SEC_READONLY1, 0x00000000U},
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* Security write protection attribute setting slave ports 2
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* {SEC_READONLY2, 0x00000000U},
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* Security write protection attribute setting slave ports 3
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* {SEC_READONLY3, 0x00000000U},
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* Security write protection attribute setting slave ports 4
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* {SEC_READONLY4, 0x00000000U},
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* Security write protection attribute setting slave ports 5
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* {SEC_READONLY5, 0x00000000U},
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* Security write protection attribute setting slave ports 6
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* {SEC_READONLY6, 0x00000000U},
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* Security write protection attribute setting slave ports 7
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* {SEC_READONLY7, 0x00000000U},
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* Security write protection attribute setting slave ports 8
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* {SEC_READONLY8, 0x00000000U},
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* Security write protection attribute setting slave ports 9
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* {SEC_READONLY9, 0x00000000U},
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* Security write protection attribute setting slave ports 10
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* {SEC_READONLY10, 0x00000000U},
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* Security write protection attribute setting slave ports 11
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* {SEC_READONLY11, 0x00000000U},
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* Security write protection attribute setting slave ports 12
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* {SEC_READONLY12, 0x00000000U},
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* Security write protection attribute setting slave ports 13
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* {SEC_READONLY13, 0x00000000U},
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* Security write protection attribute setting slave ports 14
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* {SEC_READONLY14, 0x00000000U},
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* Security write protection attribute setting slave ports 15
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* {SEC_READONLY15, 0x00000000U}
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*/
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};
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/* AXI settings */
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static const struct {
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uint32_t reg;
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uint32_t val;
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} axi[] = {
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/*
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* DRAM protection
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* AXI dram protected area division
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*/
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{AXI_DPTDIVCR0, 0x0E0403F0U},
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{AXI_DPTDIVCR1, 0x0E0407E0U},
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{AXI_DPTDIVCR2, 0x0E080000U},
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{AXI_DPTDIVCR3, 0x0E080000U},
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{AXI_DPTDIVCR4, 0x0E080000U},
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{AXI_DPTDIVCR5, 0x0E080000U},
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{AXI_DPTDIVCR6, 0x0E080000U},
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{AXI_DPTDIVCR7, 0x0E080000U},
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{AXI_DPTDIVCR8, 0x0E080000U},
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{AXI_DPTDIVCR9, 0x0E080000U},
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{AXI_DPTDIVCR10, 0x0E080000U},
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{AXI_DPTDIVCR11, 0x0E080000U},
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{AXI_DPTDIVCR12, 0x0E080000U},
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{AXI_DPTDIVCR13, 0x0E080000U},
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{AXI_DPTDIVCR14, 0x0E080000U},
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/* AXI dram protected area setting */
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{AXI_DPTCR0, 0x0E000000U},
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{AXI_DPTCR1, 0x0E000E0EU},
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{AXI_DPTCR2, 0x0E000000U},
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{AXI_DPTCR3, 0x0E000000U},
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{AXI_DPTCR4, 0x0E000000U},
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{AXI_DPTCR5, 0x0E000000U},
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{AXI_DPTCR6, 0x0E000000U},
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{AXI_DPTCR7, 0x0E000000U},
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{AXI_DPTCR8, 0x0E000000U},
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{AXI_DPTCR9, 0x0E000000U},
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{AXI_DPTCR10, 0x0E000000U},
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{AXI_DPTCR11, 0x0E000000U},
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{AXI_DPTCR12, 0x0E000000U},
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{AXI_DPTCR13, 0x0E000000U},
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{AXI_DPTCR14, 0x0E000000U},
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{AXI_DPTCR15, 0x0E000000U},
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/*
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* SRAM ptotection
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* AXI sram protected area division
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*/
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{AXI_SPTDIVCR0, 0x0E0E6304U},
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{AXI_SPTDIVCR1, 0x0E0E6360U},
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{AXI_SPTDIVCR2, 0x0E0E6360U},
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{AXI_SPTDIVCR3, 0x0E0E6360U},
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{AXI_SPTDIVCR4, 0x0E0E6360U},
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{AXI_SPTDIVCR5, 0x0E0E6360U},
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{AXI_SPTDIVCR6, 0x0E0E6360U},
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{AXI_SPTDIVCR7, 0x0E0E6360U},
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{AXI_SPTDIVCR8, 0x0E0E6360U},
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{AXI_SPTDIVCR9, 0x0E0E6360U},
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{AXI_SPTDIVCR10, 0x0E0E6360U},
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{AXI_SPTDIVCR11, 0x0E0E6360U},
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{AXI_SPTDIVCR12, 0x0E0E6360U},
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{AXI_SPTDIVCR13, 0x0E0E6360U},
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{AXI_SPTDIVCR14, 0x0E0E6360U},
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/* AXI sram protected area setting */
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{AXI_SPTCR0, 0x0E000E0EU},
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{AXI_SPTCR1, 0x0E000000U},
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{AXI_SPTCR2, 0x0E000000U},
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|
|
{AXI_SPTCR3, 0x0E000000U},
|
||
|
|
{AXI_SPTCR4, 0x0E000000U},
|
||
|
|
{AXI_SPTCR5, 0x0E000000U},
|
||
|
|
{AXI_SPTCR6, 0x0E000000U},
|
||
|
|
{AXI_SPTCR7, 0x0E000000U},
|
||
|
|
{AXI_SPTCR8, 0x0E000000U},
|
||
|
|
{AXI_SPTCR9, 0x0E000000U},
|
||
|
|
{AXI_SPTCR10, 0x0E000000U},
|
||
|
|
{AXI_SPTCR11, 0x0E000000U},
|
||
|
|
{AXI_SPTCR12, 0x0E000000U},
|
||
|
|
{AXI_SPTCR13, 0x0E000000U},
|
||
|
|
{AXI_SPTCR14, 0x0E000000U},
|
||
|
|
{AXI_SPTCR15, 0x0E000000U}
|
||
|
|
};
|
||
|
|
|
||
|
|
static void lifec_security_setting(void)
|
||
|
|
{
|
||
|
|
uint32_t i;
|
||
|
|
|
||
|
|
for (i = 0; i < ARRAY_SIZE(lifec); i++)
|
||
|
|
mmio_write_32(lifec[i].reg, lifec[i].val);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* SRAM/DRAM protection setting */
|
||
|
|
static void axi_security_setting(void)
|
||
|
|
{
|
||
|
|
uint32_t i;
|
||
|
|
|
||
|
|
for (i = 0; i < ARRAY_SIZE(axi); i++)
|
||
|
|
mmio_write_32(axi[i].reg, axi[i].val);
|
||
|
|
}
|
||
|
|
|
||
|
|
void bl2_secure_setting(void)
|
||
|
|
{
|
||
|
|
lifec_security_setting();
|
||
|
|
axi_security_setting();
|
||
|
|
rcar_micro_delay(10U);
|
||
|
|
}
|