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103 lines
3.2 KiB
103 lines
3.2 KiB
4 months ago
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SECURE_H
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#define SECURE_H
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/******************************************************************************
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* TZPC TrustZone controller
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******************************************************************************/
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#define TZPC_R0SIZE 0x0
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#define TZPC_SRAM_SECURE_4K(n) ((n) > 0x200 ? 0x200 : (n))
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#define TZPC_DECPROT1STAT 0x80c
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#define TZPC_DECPROT1SET 0x810
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#define TZPC_DECPROT1CLR 0x814
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#define TZPC_DECPROT2STAT 0x818
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#define TZPC_DECPROT2SET 0x818
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#define TZPC_DECPROT2CLR 0x820
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/**************************************************
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* sgrf reg, offset
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**************************************************/
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/*
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* soc_con0-5 start at 0x0, soc_con6-... start art 0x50
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* adjusted for the 5 lower registers
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*/
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#define SGRF_SOC_CON(n) ((((n) < 6) ? 0x0 : 0x38) + (n) * 4)
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#define SGRF_BUSDMAC_CON(n) (0x20 + (n) * 4)
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#define SGRF_CPU_CON(n) (0x40 + (n) * 4)
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#define SGRF_SOC_STATUS(n) (0x100 + (n) * 4)
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#define SGRF_FAST_BOOT_ADDR 0x120
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/* SGRF_SOC_CON0 */
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#define SGRF_FAST_BOOT_ENA BIT_WITH_WMSK(8)
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#define SGRF_FAST_BOOT_DIS WMSK_BIT(8)
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#define SGRF_PCLK_WDT_GATE BIT_WITH_WMSK(6)
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#define SGRF_PCLK_WDT_UNGATE WMSK_BIT(6)
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#define SGRF_PCLK_STIMER_GATE BIT_WITH_WMSK(4)
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#define SGRF_SOC_CON2_MST_NS 0xffe0ffe0
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#define SGRF_SOC_CON3_MST_NS 0x003f003f
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/* SGRF_SOC_CON4 */
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#define SGRF_SOC_CON4_SECURE_WMSK 0xffff0000
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#define SGRF_DDRC1_SECURE BIT_WITH_WMSK(12)
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#define SGRF_DDRC0_SECURE BIT_WITH_WMSK(11)
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#define SGRF_PMUSRAM_SECURE BIT_WITH_WMSK(8)
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#define SGRF_WDT_SECURE BIT_WITH_WMSK(7)
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#define SGRF_STIMER_SECURE BIT_WITH_WMSK(6)
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/* SGRF_SOC_CON5 */
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#define SGRF_SLV_SEC_BYPS BIT_WITH_WMSK(15)
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#define SGRF_SLV_SEC_NO_BYPS WMSK_BIT(15)
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#define SGRF_SOC_CON5_SECURE_WMSK 0x00ff0000
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/* ddr regions in SGRF_SOC_CON6 and following */
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#define SGRF_DDR_RGN_SECURE_SEL BIT_WITH_WMSK(15)
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#define SGRF_DDR_RGN_SECURE_EN BIT_WITH_WMSK(14)
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#define SGRF_DDR_RGN_ADDR_WMSK 0x0fff
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/* SGRF_SOC_CON21 */
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/* All security of the DDR RGNs are bypassed */
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#define SGRF_DDR_RGN_BYPS BIT_WITH_WMSK(15)
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#define SGRF_DDR_RGN_NO_BYPS WMSK_BIT(15)
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/* SGRF_CPU_CON0 */
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#define SGRF_DAPDEVICE_ENA BIT_WITH_WMSK(0)
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#define SGRF_DAPDEVICE_MSK WMSK_BIT(0)
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/*****************************************************************************
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* core-axi
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*****************************************************************************/
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#define CORE_AXI_SECURITY0 0x08
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#define AXI_SECURITY0_GIC BIT(0)
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/*****************************************************************************
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* secure timer
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*****************************************************************************/
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#define TIMER_LOAD_COUNT0 0x00
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#define TIMER_LOAD_COUNT1 0x04
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#define TIMER_CURRENT_VALUE0 0x08
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#define TIMER_CURRENT_VALUE1 0x0C
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#define TIMER_CONTROL_REG 0x10
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#define TIMER_INTSTATUS 0x18
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#define TIMER_EN 0x1
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#define STIMER1_BASE (STIME_BASE + 0x20)
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/* export secure operating APIs */
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void secure_watchdog_gate(void);
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void secure_watchdog_ungate(void);
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void secure_gic_init(void);
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void secure_timer_init(void);
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void secure_sgrf_init(void);
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void secure_sgrf_ddr_rgn_init(void);
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__pmusramfunc void sram_secure_timer_init(void);
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#endif /* SECURE_H */
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