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111 lines
3.2 KiB
111 lines
3.2 KiB
4 months ago
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SOC_H
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#define SOC_H
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enum plls_id {
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APLL_ID = 0,
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DPLL_ID,
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CPLL_ID,
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GPLL_ID,
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NPLL_ID,
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END_PLL_ID,
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};
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#define CYCL_24M_CNT_US(us) (24 * (us))
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#define CYCL_24M_CNT_MS(ms) ((ms) * CYCL_24M_CNT_US(1000))
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/*****************************************************************************
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* grf regs
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*****************************************************************************/
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#define GRF_UOC0_CON0 0x320
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#define GRF_UOC1_CON0 0x334
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#define GRF_UOC2_CON0 0x348
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#define GRF_SIDDQ BIT(13)
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/*****************************************************************************
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* cru reg, offset
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*****************************************************************************/
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#define CRU_SOFTRST_CON 0x1b8
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#define CRU_SOFTRSTS_CON(n) (CRU_SOFTRST_CON + ((n) * 4))
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#define CRU_SOFTRSTS_CON_CNT 11
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#define RST_DMA1_MSK 0x4
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#define RST_DMA2_MSK 0x1
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#define CRU_CLKSEL_CON 0x60
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#define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON + ((i) * 4))
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#define CRU_CLKSELS_CON_CNT 42
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#define CRU_CLKGATE_CON 0x160
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#define CRU_CLKGATES_CON(i) (CRU_CLKGATE_CON + ((i) * 4))
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#define CRU_CLKGATES_CON_CNT 18
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#define CRU_GLB_SRST_FST 0x1b0
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#define CRU_GLB_SRST_SND 0x1b4
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#define CRU_GLB_RST_CON 0x1f0
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#define CRU_CONS_GATEID(i) (16 * (i))
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#define GATE_ID(reg, bit) (((reg) * 16) + (bit))
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#define PMU_RST_MASK 0x3
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#define PMU_RST_BY_FIRST_SFT (0 << 2)
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#define PMU_RST_BY_SECOND_SFT (1 << 2)
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#define PMU_RST_NOT_BY_SFT (2 << 2)
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/***************************************************************************
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* pll
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***************************************************************************/
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#define PLL_CON_COUNT 4
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#define PLL_CONS(id, i) ((id) * 0x10 + ((i) * 4))
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#define PLL_PWR_DN_MSK BIT(1)
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#define PLL_PWR_DN REG_WMSK_BITS(1, 1, 0x1)
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#define PLL_PWR_ON REG_WMSK_BITS(0, 1, 0x1)
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#define PLL_RESET REG_WMSK_BITS(1, 5, 0x1)
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#define PLL_RESET_RESUME REG_WMSK_BITS(0, 5, 0x1)
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#define PLL_BYPASS_MSK BIT(0)
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#define PLL_BYPASS_W_MSK (PLL_BYPASS_MSK << 16)
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#define PLL_BYPASS REG_WMSK_BITS(1, 0, 0x1)
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#define PLL_NO_BYPASS REG_WMSK_BITS(0, 0, 0x1)
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#define PLL_MODE_CON 0x50
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struct deepsleep_data_s {
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uint32_t pll_con[END_PLL_ID][PLL_CON_COUNT];
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uint32_t pll_mode;
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uint32_t cru_sel_con[CRU_CLKSELS_CON_CNT];
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uint32_t cru_gate_con[CRU_CLKGATES_CON_CNT];
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};
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#define REG_W_MSK(bits_shift, msk) \
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((msk) << ((bits_shift) + 16))
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#define REG_VAL_CLRBITS(val, bits_shift, msk) \
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((val) & (~((msk) << bits_shift)))
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#define REG_SET_BITS(bits, bits_shift, msk) \
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(((bits) & (msk)) << (bits_shift))
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#define REG_WMSK_BITS(bits, bits_shift, msk) \
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(REG_W_MSK(bits_shift, msk) | \
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REG_SET_BITS(bits, bits_shift, msk))
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#define REG_SOC_WMSK 0xffff0000
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#define regs_update_bit_set(addr, shift) \
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regs_update_bits((addr), 0x1, 0x1, (shift))
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#define regs_update_bit_clr(addr, shift) \
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regs_update_bits((addr), 0x0, 0x1, (shift))
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void regs_update_bits(uintptr_t addr, uint32_t val,
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uint32_t mask, uint32_t shift);
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void clk_plls_suspend(void);
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void clk_plls_resume(void);
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void clk_gate_con_save(void);
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void clk_gate_con_disable(void);
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void clk_gate_con_restore(void);
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void clk_sel_con_save(void);
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void clk_sel_con_restore(void);
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#endif /* SOC_H */
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