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130 lines
2.8 KiB
130 lines
2.8 KiB
4 months ago
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PMU_H
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#define PMU_H
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#include <soc.h>
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struct rk3328_sleep_ddr_data {
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uint32_t pmu_debug_enable;
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uint32_t debug_iomux_save;
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uint32_t pmic_sleep_save;
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uint32_t pmu_wakeup_conf0;
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uint32_t pmu_pwrmd_com;
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uint32_t cru_mode_save;
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uint32_t clk_sel0, clk_sel1, clk_sel18,
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clk_sel20, clk_sel24, clk_sel38;
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uint32_t clk_ungt_save[CRU_CLKGATE_NUMS];
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uint32_t cru_plls_con_save[MAX_PLL][CRU_PLL_CON_NUMS];
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};
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struct rk3328_sleep_sram_data {
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uint32_t pmic_sleep_save;
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uint32_t pmic_sleep_gpio_save[2];
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uint32_t ddr_grf_con0;
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uint32_t dpll_con_save[CRU_PLL_CON_NUMS];
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uint32_t pd_sr_idle_save;
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uint32_t uart2_ier;
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};
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/*****************************************************************************
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* The ways of cores power domain contorlling
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*****************************************************************************/
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enum cores_pm_ctr_mode {
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core_pwr_pd = 0,
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core_pwr_wfi = 1,
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core_pwr_wfi_int = 2
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};
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enum pmu_cores_pm_by_wfi {
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core_pm_en = 0,
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core_pm_int_wakeup_en,
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core_pm_dis_int,
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core_pm_sft_wakeup_en
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};
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extern void *pmu_cpuson_entrypoint_start;
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extern void *pmu_cpuson_entrypoint_end;
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#define CORES_PM_DISABLE 0x0
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/*****************************************************************************
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* pmu con,reg
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*****************************************************************************/
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#define PMU_WAKEUP_CFG0 0x00
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#define PMU_PWRDN_CON 0x0c
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#define PMU_PWRDN_ST 0x10
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#define PMU_PWRMD_COM 0x18
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#define PMU_SFT_CON 0x1c
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#define PMU_INT_CON 0x20
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#define PMU_INT_ST 0x24
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#define PMU_POWER_ST 0x44
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#define PMU_CPUAPM_CON(n) (0x80 + (n) * 4)
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#define PMU_SYS_REG(n) (0xa0 + (n) * 4)
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#define CHECK_CPU_WFIE_BASE (GRF_BASE + GRF_CPU_STATUS(1))
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enum pmu_core_pwrst_shift {
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clst_cpu_wfe = 0,
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clst_cpu_wfi = 4,
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};
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#define clstl_cpu_wfe (clst_cpu_wfe)
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#define clstb_cpu_wfe (clst_cpu_wfe)
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enum pmu_pd_id {
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PD_CPU0 = 0,
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PD_CPU1,
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PD_CPU2,
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PD_CPU3,
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};
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enum pmu_power_mode_common {
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pmu_mode_en = 0,
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sref_enter_en,
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global_int_disable_cfg,
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cpu0_pd_en,
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wait_wakeup_begin_cfg = 4,
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l2_flush_en,
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l2_idle_en,
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ddrio_ret_de_req,
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ddrio_ret_en = 8,
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};
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enum pmu_sft_con {
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upctl_c_sysreq_cfg = 0,
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l2flushreq_req,
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ddr_io_ret_cfg,
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pmu_sft_ret_cfg,
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};
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#define CKECK_WFE_MSK 0x1
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#define CKECK_WFI_MSK 0x10
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#define CKECK_WFEI_MSK 0x11
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#define PD_CTR_LOOP 500
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#define CHK_CPU_LOOP 500
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#define MAX_WAIT_CONUT 1000
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#define WAKEUP_INT_CLUSTER_EN 0x1
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#define PMIC_SLEEP_REG 0x34
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#define PLL_IS_NORM_MODE(mode, pll_id) \
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((mode & (PLL_NORM_MODE(pll_id)) & 0xffff) != 0)
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#define CTLR_ENABLE_G1_BIT BIT(1)
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#define UART_FIFO_EMPTY BIT(6)
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#define UART_IER 0x04
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#define UART_FCR 0x08
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#define UART_LSR 0x14
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#define UART_INT_DISABLE 0x00
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#define UART_FIFO_RESET 0x07
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#endif /* PMU_H */
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