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152 lines
4.1 KiB
152 lines
4.1 KiB
4 months ago
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/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef RK3328_DEF_H
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#define RK3328_DEF_H
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#define MAJOR_VERSION (1)
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#define MINOR_VERSION (2)
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#define SIZE_K(n) ((n) * 1024)
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/* Special value used to verify platform parameters from BL2 to BL3-1 */
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#define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
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#define UART0_BASE 0xff110000
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#define UART0_SIZE SIZE_K(64)
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#define UART1_BASE 0xff120000
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#define UART1_SIZE SIZE_K(64)
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#define UART2_BASE 0xff130000
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#define UART2_SIZE SIZE_K(64)
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#define PMU_BASE 0xff140000
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#define PMU_SIZE SIZE_K(64)
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#define SGRF_BASE 0xff0d0000
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#define SGRF_SIZE SIZE_K(64)
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#define CRU_BASE 0xff440000
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#define CRU_SIZE SIZE_K(64)
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#define GRF_BASE 0xff100000
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#define GRF_SIZE SIZE_K(64)
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#define GPIO0_BASE 0xff210000
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#define GPIO0_SIZE SIZE_K(32)
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#define GPIO1_BASE 0xff220000
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#define GPIO1_SIZE SIZE_K(32)
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#define GPIO2_BASE 0xff230000
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#define GPIO2_SIZE SIZE_K(64)
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#define GPIO3_BASE 0xff240000
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#define GPIO3_SIZE SIZE_K(64)
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#define STIME_BASE 0xff1d0000
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#define STIME_SIZE SIZE_K(64)
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#define INTMEM_BASE 0xff090000
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#define INTMEM_SIZE SIZE_K(32)
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#define SRAM_LDS_BASE (INTMEM_BASE + SIZE_K(4))
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#define SRAM_LDS_SIZE (INTMEM_SIZE - SIZE_K(4))
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#define PMUSRAM_BASE INTMEM_BASE
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#define PMUSRAM_SIZE SIZE_K(4)
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#define PMUSRAM_RSIZE SIZE_K(4)
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#define VOP_BASE 0xff370000
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#define VOP_SIZE SIZE_K(16)
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#define DDR_PHY_BASE 0xff400000
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#define DDR_PHY_SIZE SIZE_K(4)
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#define SERVER_MSCH_BASE 0xff720000
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#define SERVER_MSCH_SIZE SIZE_K(4)
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#define DDR_UPCTL_BASE 0xff780000
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#define DDR_UPCTL_SIZE SIZE_K(12)
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#define DDR_MONITOR_BASE 0xff790000
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#define DDR_MONITOR_SIZE SIZE_K(4)
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#define FIREWALL_DDR_BASE 0xff7c0000
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#define FIREWALL_DDR_SIZE SIZE_K(64)
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#define FIREWALL_CFG_BASE 0xff7d0000
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#define FIREWALL_CFG_SIZE SIZE_K(64)
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#define GIC400_BASE 0xff810000
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#define GIC400_SIZE SIZE_K(64)
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#define DDR_GRF_BASE 0xff798000
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#define DDR_GRF_SIZE SIZE_K(16)
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#define PWM_BASE 0xff1b0000
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#define PWM_SIZE SIZE_K(64)
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#define DDR_PARAM_BASE 0x02000000
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#define DDR_PARAM_SIZE SIZE_K(4)
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#define EFUSE8_BASE 0xff260000
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#define EFUSE8_SIZE SIZE_K(4)
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#define EFUSE32_BASE 0xff0b0000
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#define EFUSE32_SIZE SIZE_K(4)
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/**************************************************************************
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* UART related constants
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**************************************************************************/
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#define RK3328_BAUDRATE 1500000
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#define RK3328_UART_CLOCK 24000000
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/******************************************************************************
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* System counter frequency related constants
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******************************************************************************/
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#define SYS_COUNTER_FREQ_IN_TICKS 24000000U
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#define SYS_COUNTER_FREQ_IN_MHZ 24
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/******************************************************************************
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* GIC-400 & interrupt handling related constants
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******************************************************************************/
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/* Base rk_platform compatible GIC memory map */
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#define RK3328_GICD_BASE (GIC400_BASE + 0x1000)
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#define RK3328_GICC_BASE (GIC400_BASE + 0x2000)
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#define RK3328_GICR_BASE 0 /* no GICR in GIC-400 */
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/******************************************************************************
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* sgi, ppi
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******************************************************************************/
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#define RK_IRQ_SEC_PHY_TIMER 29
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#define RK_IRQ_SEC_SGI_0 8
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#define RK_IRQ_SEC_SGI_1 9
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#define RK_IRQ_SEC_SGI_2 10
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#define RK_IRQ_SEC_SGI_3 11
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#define RK_IRQ_SEC_SGI_4 12
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#define RK_IRQ_SEC_SGI_5 13
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#define RK_IRQ_SEC_SGI_6 14
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#define RK_IRQ_SEC_SGI_7 15
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/*
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* Define a list of Group 0 interrupts.
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*/
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#define PLAT_RK_GICV2_G0_IRQS \
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INTR_PROP_DESC(RK_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(RK_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL)
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#define SHARE_MEM_BASE 0x100000/* [1MB, 1MB+60K]*/
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#define SHARE_MEM_PAGE_NUM 15
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#define SHARE_MEM_SIZE SIZE_K(SHARE_MEM_PAGE_NUM * 4)
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#endif /* RK3328_DEF_H */
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