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208 lines
3.9 KiB
208 lines
3.9 KiB
4 months ago
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PMU_H
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#define PMU_H
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/* Allocate sp reginon in pmusram */
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#define PSRAM_SP_SIZE 0x80
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#define PSRAM_SP_BOTTOM (PSRAM_SP_TOP - PSRAM_SP_SIZE)
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/*****************************************************************************
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* pmu con,reg
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*****************************************************************************/
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#define PMU_WKUP_CFG0 0x0
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#define PMU_WKUP_CFG1 0x4
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#define PMU_WKUP_CFG2 0x8
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#define PMU_TIMEOUT_CNT 0x7c
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#define PMU_PWRDN_CON 0xc
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#define PMU_PWRDN_ST 0x10
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#define PMU_CORE_PWR_ST 0x38
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#define PMU_PWRMD_CORE 0x14
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#define PMU_PWRMD_COM 0x18
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#define PMU_SFT_CON 0x1c
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#define PMU_BUS_IDE_REQ 0x3c
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#define PMU_BUS_IDE_ST 0x40
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#define PMU_OSC_CNT 0x48
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#define PMU_PLLLOCK_CNT 0x4c
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#define PMU_PLLRST_CNT 0x50
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#define PMU_STABLE_CNT 0x54
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#define PMU_DDRIO_PWR_CNT 0x58
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#define PMU_WKUPRST_CNT 0x5c
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enum pmu_powermode_core {
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pmu_mdcr_global_int_dis = 0,
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pmu_mdcr_core_src_gt,
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pmu_mdcr_clr_cci,
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pmu_mdcr_cpu0_pd,
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pmu_mdcr_clr_clst_l = 4,
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pmu_mdcr_clr_core,
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pmu_mdcr_scu_l_pd,
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pmu_mdcr_core_pd,
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pmu_mdcr_l2_idle = 8,
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pmu_mdcr_l2_flush
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};
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/*
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* the shift of bits for cores status
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*/
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enum pmu_core_pwrst_shift {
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clstl_cpu_wfe = 2,
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clstl_cpu_wfi = 6,
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clstb_cpu_wfe = 12,
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clstb_cpu_wfi = 16
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};
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enum pmu_pdid {
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PD_CPUL0 = 0,
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PD_CPUL1,
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PD_CPUL2,
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PD_CPUL3,
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PD_SCUL,
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PD_CPUB0 = 5,
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PD_CPUB1,
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PD_CPUB2,
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PD_CPUB3,
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PD_SCUB = 9,
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PD_PERI = 13,
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PD_VIDEO,
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PD_VIO,
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PD_GPU0,
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PD_GPU1,
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PD_END
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};
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enum pmu_bus_ide {
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bus_ide_req_clst_l = 0,
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bus_ide_req_clst_b,
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bus_ide_req_gpu,
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bus_ide_req_core,
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bus_ide_req_bus = 4,
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bus_ide_req_dma,
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bus_ide_req_peri,
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bus_ide_req_video,
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bus_ide_req_vio = 8,
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bus_ide_req_res0,
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bus_ide_req_cxcs,
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bus_ide_req_alive,
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bus_ide_req_pmu = 12,
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bus_ide_req_msch,
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bus_ide_req_cci,
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bus_ide_req_cci400 = 15,
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bus_ide_req_end
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};
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enum pmu_powermode_common {
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pmu_mode_en = 0,
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pmu_mode_res0,
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pmu_mode_bus_pd,
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pmu_mode_wkup_rst,
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pmu_mode_pll_pd = 4,
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pmu_mode_pwr_off,
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pmu_mode_pmu_use_if,
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pmu_mode_pmu_alive_use_if,
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pmu_mode_osc_dis = 8,
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pmu_mode_input_clamp,
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pmu_mode_sref_enter,
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pmu_mode_ddrc_gt,
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pmu_mode_ddrio_ret = 12,
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pmu_mode_ddrio_ret_deq,
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pmu_mode_clr_pmu,
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pmu_mode_clr_alive,
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pmu_mode_clr_bus = 16,
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pmu_mode_clr_dma,
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pmu_mode_clr_msch,
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pmu_mode_clr_peri,
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pmu_mode_clr_video = 20,
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pmu_mode_clr_vio,
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pmu_mode_clr_gpu,
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pmu_mode_clr_mcu,
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pmu_mode_clr_cxcs = 24,
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pmu_mode_clr_cci400,
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pmu_mode_res1,
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pmu_mode_res2,
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pmu_mode_res3 = 28,
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pmu_mode_mclst
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};
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enum pmu_core_power_st {
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clst_l_cpu_wfe = 2,
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clst_l_cpu_wfi = 6,
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clst_b_l2_flsh_done = 10,
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clst_b_l2_wfi = 11,
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clst_b_cpu_wfe = 12,
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clst_b_cpu_wfi = 16,
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mcu_sleeping = 20,
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};
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enum pmu_sft_con {
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pmu_sft_acinactm_clst_b = 5,
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pmu_sft_l2flsh_clst_b,
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pmu_sft_glbl_int_dis_b = 9,
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pmu_sft_ddrio_ret_cfg = 11,
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};
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enum pmu_wkup_cfg2 {
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pmu_cluster_l_wkup_en = 0,
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pmu_cluster_b_wkup_en,
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pmu_gpio_wkup_en,
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pmu_sdio_wkup_en,
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pmu_sdmmc_wkup_en,
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pmu_sim_wkup_en,
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pmu_timer_wkup_en,
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pmu_usbdev_wkup_en,
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pmu_sft_wkup_en,
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pmu_wdt_mcu_wkup_en,
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pmu_timeout_wkup_en,
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};
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enum pmu_bus_idle_st {
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pmu_idle_ack_cluster_l = 0,
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pmu_idle_ack_cluster_b,
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pmu_idle_ack_gpu,
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pmu_idle_ack_core,
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pmu_idle_ack_bus,
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pmu_idle_ack_dma,
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pmu_idle_ack_peri,
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pmu_idle_ack_video,
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pmu_idle_ack_vio,
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pmu_idle_ack_cci = 10,
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pmu_idle_ack_msch,
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pmu_idle_ack_alive,
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pmu_idle_ack_pmu,
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pmu_idle_ack_cxcs,
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pmu_idle_ack_cci400,
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pmu_inactive_cluster_l,
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pmu_inactive_cluster_b,
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pmu_idle_gpu,
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pmu_idle_core,
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pmu_idle_bus,
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pmu_idle_dma,
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pmu_idle_peri,
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pmu_idle_video,
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pmu_idle_vio,
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pmu_idle_cci = 26,
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pmu_idle_msch,
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pmu_idle_alive,
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pmu_idle_pmu,
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pmu_active_cxcs,
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pmu_active_cci,
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};
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#define PM_PWRDM_CPUSB_MSK (0xf << 5)
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#define CKECK_WFE_MSK 0x1
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#define CKECK_WFI_MSK 0x10
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#define CKECK_WFEI_MSK 0x11
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#define PD_CTR_LOOP 500
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#define CHK_CPU_LOOP 500
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#define MAX_WAIT_CONUT 1000
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#endif /* PMU_H */
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