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32 lines
737 B
32 lines
737 B
7 months ago
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/*
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* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SYNQUACER_PLAT_LD_S__
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#define SYNQUACER_PLAT_LD_S__
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#include <lib/xlat_tables/xlat_tables_defs.h>
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#define SPM_SHIM_EXCEPTIONS_VMA SP_DRAM
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MEMORY {
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SP_DRAM (rw): ORIGIN = PLAT_SQ_SP_PRIV_BASE, LENGTH = PLAT_SQ_SP_PRIV_SIZE
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}
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SECTIONS
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{
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/*
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* Put the page tables in secure DRAM so that the PTW can make cacheable
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* accesses, as the core SPM code expects. (The SRAM on SynQuacer does
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* not support inner shareable WBWA mappings so it is mapped normal
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* non-cacheable)
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*/
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sp_xlat_table (NOLOAD) : ALIGN(PAGE_SIZE) {
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*(sp_xlat_table)
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} >SP_DRAM
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}
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#endif /* SYNQUACER_PLAT_LD_S__ */
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