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130 lines
4.8 KiB
130 lines
4.8 KiB
4 months ago
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#!/usr/bin/env python
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# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
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from __future__ import print_function
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from capstone import *
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from capstone.arm64 import *
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from xprint import to_hex, to_x
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ARM64_CODE = b"\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c"
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all_tests = (
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(CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64"),
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)
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def print_insn_detail(insn):
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# print address, mnemonic and operands
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print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
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# "data" instruction generated by SKIPDATA option has no detail
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if insn.id == 0:
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return
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if len(insn.operands) > 0:
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print("\top_count: %u" % len(insn.operands))
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c = -1
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for i in insn.operands:
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c += 1
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if i.type == ARM64_OP_REG:
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print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
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if i.type == ARM64_OP_IMM:
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print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
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if i.type == ARM64_OP_CIMM:
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print("\t\toperands[%u].type: C-IMM = %u" % (c, i.imm))
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if i.type == ARM64_OP_FP:
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print("\t\toperands[%u].type: FP = %f" % (c, i.fp))
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if i.type == ARM64_OP_MEM:
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print("\t\toperands[%u].type: MEM" % c)
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if i.mem.base != 0:
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print("\t\t\toperands[%u].mem.base: REG = %s" \
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% (c, insn.reg_name(i.mem.base)))
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if i.mem.index != 0:
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print("\t\t\toperands[%u].mem.index: REG = %s" \
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% (c, insn.reg_name(i.mem.index)))
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if i.mem.disp != 0:
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print("\t\t\toperands[%u].mem.disp: 0x%s" \
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% (c, to_x(i.mem.disp)))
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if i.type == ARM64_OP_REG_MRS:
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print("\t\toperands[%u].type: REG_MRS = 0x%x" % (c, i.reg))
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if i.type == ARM64_OP_REG_MSR:
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print("\t\toperands[%u].type: REG_MSR = 0x%x" % (c, i.reg))
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if i.type == ARM64_OP_PSTATE:
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print("\t\toperands[%u].type: PSTATE = 0x%x" % (c, i.pstate))
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if i.type == ARM64_OP_SYS:
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print("\t\toperands[%u].type: SYS = 0x%x" % (c, i.sys))
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if i.type == ARM64_OP_PREFETCH:
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print("\t\toperands[%u].type: PREFETCH = 0x%x" % (c, i.prefetch))
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if i.type == ARM64_OP_BARRIER:
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print("\t\toperands[%u].type: BARRIER = 0x%x" % (c, i.barrier))
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if i.shift.type != ARM64_SFT_INVALID and i.shift.value:
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print("\t\t\tShift: type = %u, value = %u" % (i.shift.type, i.shift.value))
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if i.ext != ARM64_EXT_INVALID:
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print("\t\t\tExt: %u" % i.ext)
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if i.vas != ARM64_VAS_INVALID:
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print("\t\t\tVector Arrangement Specifier: 0x%x" % i.vas)
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if i.vess != ARM64_VESS_INVALID:
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print("\t\t\tVector Element Size Specifier: %u" % i.vess)
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if i.vector_index != -1:
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print("\t\t\tVector Index: %u" % i.vector_index)
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if i.access == CS_AC_READ:
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print("\t\toperands[%u].access: READ\n" % (c))
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elif i.access == CS_AC_WRITE:
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print("\t\toperands[%u].access: WRITE\n" % (c))
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elif i.access == CS_AC_READ | CS_AC_WRITE:
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print("\t\toperands[%u].access: READ | WRITE\n" % (c))
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if insn.writeback:
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print("\tWrite-back: True")
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if not insn.cc in [ARM64_CC_AL, ARM64_CC_INVALID]:
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print("\tCode-condition: %u" % insn.cc)
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if insn.update_flags:
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print("\tUpdate-flags: True")
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(regs_read, regs_write) = insn.regs_access()
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if len(regs_read) > 0:
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print("\tRegisters read:", end="")
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for r in regs_read:
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print(" %s" %(insn.reg_name(r)), end="")
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print("")
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if len(regs_write) > 0:
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print("\tRegisters modified:", end="")
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for r in regs_write:
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print(" %s" %(insn.reg_name(r)), end="")
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print("")
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# ## Test class Cs
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def test_class():
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for (arch, mode, code, comment) in all_tests:
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print("*" * 16)
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print("Platform: %s" % comment)
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print("Code: %s" % to_hex(code))
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print("Disasm:")
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try:
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md = Cs(arch, mode)
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md.detail = True
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for insn in md.disasm(code, 0x2c):
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print_insn_detail(insn)
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print ()
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print("0x%x:\n" % (insn.address + insn.size))
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except CsError as e:
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print("ERROR: %s" % e)
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if __name__ == '__main__':
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test_class()
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