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593 lines
17 KiB
593 lines
17 KiB
4 months ago
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: cvt_f32_ubyte0_lshr_0
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: cvt_f32_ubyte0_lshr_0
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; CHECK: liveins: $vgpr0
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; CHECK: %arg:_(s32) = COPY $vgpr0
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; CHECK: %result:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 %arg
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; CHECK: $vgpr0 = COPY %result(s32)
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%arg:_(s32) = COPY $vgpr0
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%shiftamt:_(s32) = G_CONSTANT i32 0
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%shift:_(s32) = G_LSHR %arg, %shiftamt
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%result:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 %shift
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$vgpr0 = COPY %result
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...
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---
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name: cvt_f32_ubyte0_lshr_8
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: cvt_f32_ubyte0_lshr_8
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; CHECK: liveins: $vgpr0
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; CHECK: %arg:_(s32) = COPY $vgpr0
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; CHECK: %result:_(s32) = G_AMDGPU_CVT_F32_UBYTE1 %arg
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; CHECK: $vgpr0 = COPY %result(s32)
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%arg:_(s32) = COPY $vgpr0
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%shiftamt:_(s32) = G_CONSTANT i32 8
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%shift:_(s32) = G_LSHR %arg, %shiftamt
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%result:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 %shift
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$vgpr0 = COPY %result
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...
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---
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name: cvt_f32_ubyte0_lshr_16
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: cvt_f32_ubyte0_lshr_16
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; CHECK: liveins: $vgpr0
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; CHECK: %arg:_(s32) = COPY $vgpr0
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; CHECK: %result:_(s32) = G_AMDGPU_CVT_F32_UBYTE2 %arg
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; CHECK: $vgpr0 = COPY %result(s32)
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%arg:_(s32) = COPY $vgpr0
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%shiftamt:_(s32) = G_CONSTANT i32 16
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%shift:_(s32) = G_LSHR %arg, %shiftamt
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%result:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 %shift
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$vgpr0 = COPY %result
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...
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---
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name: cvt_f32_ubyte0_lshr_24
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: cvt_f32_ubyte0_lshr_24
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; CHECK: liveins: $vgpr0
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; CHECK: %arg:_(s32) = COPY $vgpr0
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; CHECK: %result:_(s32) = G_AMDGPU_CVT_F32_UBYTE3 %arg
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; CHECK: $vgpr0 = COPY %result(s32)
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%arg:_(s32) = COPY $vgpr0
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%shiftamt:_(s32) = G_CONSTANT i32 24
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%shift:_(s32) = G_LSHR %arg, %shiftamt
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%result:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 %shift
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$vgpr0 = COPY %result
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...
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---
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name: cvt_f32_ubyte1_lshr_8
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: cvt_f32_ubyte1_lshr_8
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; CHECK: liveins: $vgpr0
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; CHECK: %arg:_(s32) = COPY $vgpr0
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; CHECK: %result:_(s32) = G_AMDGPU_CVT_F32_UBYTE2 %arg
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; CHECK: $vgpr0 = COPY %result(s32)
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%arg:_(s32) = COPY $vgpr0
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%shiftamt:_(s32) = G_CONSTANT i32 8
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%shift:_(s32) = G_LSHR %arg, %shiftamt
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%result:_(s32) = G_AMDGPU_CVT_F32_UBYTE1 %shift
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$vgpr0 = COPY %result
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...
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---
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name: cvt_f32_ubyte1_lshr_16
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: cvt_f32_ubyte1_lshr_16
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; CHECK: liveins: $vgpr0
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; CHECK: %arg:_(s32) = COPY $vgpr0
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; CHECK: %result:_(s32) = G_AMDGPU_CVT_F32_UBYTE3 %arg
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; CHECK: $vgpr0 = COPY %result(s32)
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%arg:_(s32) = COPY $vgpr0
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%shiftamt:_(s32) = G_CONSTANT i32 16
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%shift:_(s32) = G_LSHR %arg, %shiftamt
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%result:_(s32) = G_AMDGPU_CVT_F32_UBYTE1 %shift
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$vgpr0 = COPY %result
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...
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---
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name: cvt_f32_ubyte1_lshr_24
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: cvt_f32_ubyte1_lshr_24
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; CHECK: liveins: $vgpr0
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; CHECK: %arg:_(s32) = COPY $vgpr0
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; CHECK: %shiftamt:_(s32) = G_CONSTANT i32 24
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; CHECK: %shift:_(s32) = G_LSHR %arg, %shiftamt(s32)
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; CHECK: %result:_(s32) = G_AMDGPU_CVT_F32_UBYTE1 %shift
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; CHECK: $vgpr0 = COPY %result(s32)
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%arg:_(s32) = COPY $vgpr0
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%shiftamt:_(s32) = G_CONSTANT i32 24
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%shift:_(s32) = G_LSHR %arg, %shiftamt
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%result:_(s32) = G_AMDGPU_CVT_F32_UBYTE1 %shift
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$vgpr0 = COPY %result
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...
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---
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name: cvt_f32_ubyte2_lshr_8
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: cvt_f32_ubyte2_lshr_8
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; CHECK: liveins: $vgpr0
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; CHECK: %arg:_(s32) = COPY $vgpr0
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; CHECK: %result:_(s32) = G_AMDGPU_CVT_F32_UBYTE3 %arg
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; CHECK: $vgpr0 = COPY %result(s32)
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%arg:_(s32) = COPY $vgpr0
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%shiftamt:_(s32) = G_CONSTANT i32 8
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%shift:_(s32) = G_LSHR %arg, %shiftamt
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%result:_(s32) = G_AMDGPU_CVT_F32_UBYTE2 %shift
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$vgpr0 = COPY %result
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...
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---
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name: cvt_f32_ubyte2_lshr_16
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: cvt_f32_ubyte2_lshr_16
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; CHECK: liveins: $vgpr0
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; CHECK: %arg:_(s32) = COPY $vgpr0
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; CHECK: %shiftamt:_(s32) = G_CONSTANT i32 16
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; CHECK: %shift:_(s32) = G_LSHR %arg, %shiftamt(s32)
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; CHECK: %result:_(s32) = G_AMDGPU_CVT_F32_UBYTE2 %shift
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; CHECK: $vgpr0 = COPY %result(s32)
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%arg:_(s32) = COPY $vgpr0
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%shiftamt:_(s32) = G_CONSTANT i32 16
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%shift:_(s32) = G_LSHR %arg, %shiftamt
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%result:_(s32) = G_AMDGPU_CVT_F32_UBYTE2 %shift
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$vgpr0 = COPY %result
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...
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---
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name: cvt_f32_ubyte2_lshr_24
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: cvt_f32_ubyte2_lshr_24
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; CHECK: liveins: $vgpr0
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; CHECK: %arg:_(s32) = COPY $vgpr0
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; CHECK: %shiftamt:_(s32) = G_CONSTANT i32 24
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; CHECK: %shift:_(s32) = G_LSHR %arg, %shiftamt(s32)
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; CHECK: %result:_(s32) = G_AMDGPU_CVT_F32_UBYTE2 %shift
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; CHECK: $vgpr0 = COPY %result(s32)
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%arg:_(s32) = COPY $vgpr0
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%shiftamt:_(s32) = G_CONSTANT i32 24
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%shift:_(s32) = G_LSHR %arg, %shiftamt
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%result:_(s32) = G_AMDGPU_CVT_F32_UBYTE2 %shift
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$vgpr0 = COPY %result
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...
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---
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name: cvt_f32_ubyte3_lshr_8
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: cvt_f32_ubyte3_lshr_8
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; CHECK: liveins: $vgpr0
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; CHECK: %arg:_(s32) = COPY $vgpr0
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; CHECK: %shiftamt:_(s32) = G_CONSTANT i32 8
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; CHECK: %shift:_(s32) = G_LSHR %arg, %shiftamt(s32)
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; CHECK: %result:_(s32) = G_AMDGPU_CVT_F32_UBYTE3 %shift
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; CHECK: $vgpr0 = COPY %result(s32)
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%arg:_(s32) = COPY $vgpr0
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%shiftamt:_(s32) = G_CONSTANT i32 8
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%shift:_(s32) = G_LSHR %arg, %shiftamt
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%result:_(s32) = G_AMDGPU_CVT_F32_UBYTE3 %shift
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$vgpr0 = COPY %result
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...
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---
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name: cvt_f32_ubyte0_zext_lshr_8
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: cvt_f32_ubyte0_zext_lshr_8
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; CHECK: liveins: $vgpr0
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; CHECK: %arg:_(s32) = COPY $vgpr0
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; CHECK: %result:_(s32) = G_AMDGPU_CVT_F32_UBYTE1 %arg
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; CHECK: $vgpr0 = COPY %result(s32)
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%arg:_(s32) = COPY $vgpr0
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%trunc:_(s16) = G_TRUNC %arg
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%shiftamt:_(s32) = G_CONSTANT i32 8
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%shift:_(s16) = G_LSHR %trunc, %shiftamt
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%zext:_(s32) = G_ZEXT %shift
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%result:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 %zext
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$vgpr0 = COPY %result
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...
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---
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name: cvt_f32_ubyte0_zext_lshr_16
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tracksRegLiveness: true
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||
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body: |
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||
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bb.0:
|
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liveins: $vgpr0
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; CHECK-LABEL: name: cvt_f32_ubyte0_zext_lshr_16
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; CHECK: liveins: $vgpr0
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; CHECK: %arg:_(s32) = COPY $vgpr0
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||
|
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; CHECK: %result:_(s32) = G_AMDGPU_CVT_F32_UBYTE2 %arg
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||
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; CHECK: $vgpr0 = COPY %result(s32)
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||
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%arg:_(s32) = COPY $vgpr0
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||
|
|
%trunc:_(s16) = G_TRUNC %arg
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||
|
|
%shiftamt:_(s32) = G_CONSTANT i32 16
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||
|
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%shift:_(s16) = G_LSHR %trunc, %shiftamt
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||
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%zext:_(s32) = G_ZEXT %shift
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||
|
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%result:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 %zext
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||
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$vgpr0 = COPY %result
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||
|
|
...
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||
|
|
|
||
|
|
---
|
||
|
|
name: cvt_f32_ubyte0_zext_lshr_24
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||
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tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $vgpr0
|
||
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|
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||
|
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; CHECK-LABEL: name: cvt_f32_ubyte0_zext_lshr_24
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||
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; CHECK: liveins: $vgpr0
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||
|
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; CHECK: %arg:_(s32) = COPY $vgpr0
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||
|
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; CHECK: %result:_(s32) = G_AMDGPU_CVT_F32_UBYTE3 %arg
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||
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; CHECK: $vgpr0 = COPY %result(s32)
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||
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%arg:_(s32) = COPY $vgpr0
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||
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%trunc:_(s16) = G_TRUNC %arg
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||
|
|
%shiftamt:_(s32) = G_CONSTANT i32 24
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||
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%shift:_(s16) = G_LSHR %trunc, %shiftamt
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||
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%zext:_(s32) = G_ZEXT %shift
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||
|
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%result:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 %zext
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||
|
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$vgpr0 = COPY %result
|
||
|
|
...
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||
|
|
|
||
|
|
---
|
||
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|
name: cvt_f32_ubyte1_zext_lshr_8
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||
|
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tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
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liveins: $vgpr0
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||
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||
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; CHECK-LABEL: name: cvt_f32_ubyte1_zext_lshr_8
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||
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; CHECK: liveins: $vgpr0
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; CHECK: %arg:_(s32) = COPY $vgpr0
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; CHECK: %result:_(s32) = G_AMDGPU_CVT_F32_UBYTE2 %arg
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; CHECK: $vgpr0 = COPY %result(s32)
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%arg:_(s32) = COPY $vgpr0
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%trunc:_(s16) = G_TRUNC %arg
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%shiftamt:_(s32) = G_CONSTANT i32 8
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%shift:_(s16) = G_LSHR %trunc, %shiftamt
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%zext:_(s32) = G_ZEXT %shift
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||
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%result:_(s32) = G_AMDGPU_CVT_F32_UBYTE1 %zext
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$vgpr0 = COPY %result
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||
|
|
...
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||
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|
||
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|
---
|
||
|
|
name: cvt_f32_ubyte0_shl_8
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||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $vgpr0
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: cvt_f32_ubyte0_shl_8
|
||
|
|
; CHECK: liveins: $vgpr0
|
||
|
|
; CHECK: %arg:_(s32) = COPY $vgpr0
|
||
|
|
; CHECK: %shiftamt:_(s32) = G_CONSTANT i32 8
|
||
|
|
; CHECK: %shift:_(s32) = G_SHL %arg, %shiftamt(s32)
|
||
|
|
; CHECK: %result:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 %shift
|
||
|
|
; CHECK: $vgpr0 = COPY %result(s32)
|
||
|
|
%arg:_(s32) = COPY $vgpr0
|
||
|
|
%shiftamt:_(s32) = G_CONSTANT i32 8
|
||
|
|
%shift:_(s32) = G_SHL %arg, %shiftamt
|
||
|
|
%result:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 %shift
|
||
|
|
$vgpr0 = COPY %result
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: cvt_f32_ubyte1_shl_8
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $vgpr0
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: cvt_f32_ubyte1_shl_8
|
||
|
|
; CHECK: liveins: $vgpr0
|
||
|
|
; CHECK: %arg:_(s32) = COPY $vgpr0
|
||
|
|
; CHECK: %shiftamt:_(s32) = G_CONSTANT i32 8
|
||
|
|
; CHECK: %shift:_(s32) = G_SHL %arg, %shiftamt(s32)
|
||
|
|
; CHECK: %result:_(s32) = G_AMDGPU_CVT_F32_UBYTE1 %shift
|
||
|
|
; CHECK: $vgpr0 = COPY %result(s32)
|
||
|
|
%arg:_(s32) = COPY $vgpr0
|
||
|
|
%shiftamt:_(s32) = G_CONSTANT i32 8
|
||
|
|
%shift:_(s32) = G_SHL %arg, %shiftamt
|
||
|
|
%result:_(s32) = G_AMDGPU_CVT_F32_UBYTE1 %shift
|
||
|
|
$vgpr0 = COPY %result
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: cvt_f32_ubyte2_shl_8
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $vgpr0
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: cvt_f32_ubyte2_shl_8
|
||
|
|
; CHECK: liveins: $vgpr0
|
||
|
|
; CHECK: %arg:_(s32) = COPY $vgpr0
|
||
|
|
; CHECK: %result:_(s32) = G_AMDGPU_CVT_F32_UBYTE1 %arg
|
||
|
|
; CHECK: $vgpr0 = COPY %result(s32)
|
||
|
|
%arg:_(s32) = COPY $vgpr0
|
||
|
|
%shiftamt:_(s32) = G_CONSTANT i32 8
|
||
|
|
%shift:_(s32) = G_SHL %arg, %shiftamt
|
||
|
|
%result:_(s32) = G_AMDGPU_CVT_F32_UBYTE2 %shift
|
||
|
|
$vgpr0 = COPY %result
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: cvt_f32_ubyte3_shl_8
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $vgpr0
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: cvt_f32_ubyte3_shl_8
|
||
|
|
; CHECK: liveins: $vgpr0
|
||
|
|
; CHECK: %arg:_(s32) = COPY $vgpr0
|
||
|
|
; CHECK: %result:_(s32) = G_AMDGPU_CVT_F32_UBYTE2 %arg
|
||
|
|
; CHECK: $vgpr0 = COPY %result(s32)
|
||
|
|
%arg:_(s32) = COPY $vgpr0
|
||
|
|
%shiftamt:_(s32) = G_CONSTANT i32 8
|
||
|
|
%shift:_(s32) = G_SHL %arg, %shiftamt
|
||
|
|
%result:_(s32) = G_AMDGPU_CVT_F32_UBYTE3 %shift
|
||
|
|
$vgpr0 = COPY %result
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: cvt_f32_ubyte0_shl_16
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $vgpr0
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: cvt_f32_ubyte0_shl_16
|
||
|
|
; CHECK: liveins: $vgpr0
|
||
|
|
; CHECK: %arg:_(s32) = COPY $vgpr0
|
||
|
|
; CHECK: %shiftamt:_(s32) = G_CONSTANT i32 16
|
||
|
|
; CHECK: %shift:_(s32) = G_SHL %arg, %shiftamt(s32)
|
||
|
|
; CHECK: %result:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 %shift
|
||
|
|
; CHECK: $vgpr0 = COPY %result(s32)
|
||
|
|
%arg:_(s32) = COPY $vgpr0
|
||
|
|
%shiftamt:_(s32) = G_CONSTANT i32 16
|
||
|
|
%shift:_(s32) = G_SHL %arg, %shiftamt
|
||
|
|
%result:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 %shift
|
||
|
|
$vgpr0 = COPY %result
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: cvt_f32_ubyte1_shl_16
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $vgpr0
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: cvt_f32_ubyte1_shl_16
|
||
|
|
; CHECK: liveins: $vgpr0
|
||
|
|
; CHECK: %arg:_(s32) = COPY $vgpr0
|
||
|
|
; CHECK: %shiftamt:_(s32) = G_CONSTANT i32 16
|
||
|
|
; CHECK: %shift:_(s32) = G_SHL %arg, %shiftamt(s32)
|
||
|
|
; CHECK: %result:_(s32) = G_AMDGPU_CVT_F32_UBYTE1 %shift
|
||
|
|
; CHECK: $vgpr0 = COPY %result(s32)
|
||
|
|
%arg:_(s32) = COPY $vgpr0
|
||
|
|
%shiftamt:_(s32) = G_CONSTANT i32 16
|
||
|
|
%shift:_(s32) = G_SHL %arg, %shiftamt
|
||
|
|
%result:_(s32) = G_AMDGPU_CVT_F32_UBYTE1 %shift
|
||
|
|
$vgpr0 = COPY %result
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: cvt_f32_ubyte2_shl_16
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $vgpr0
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: cvt_f32_ubyte2_shl_16
|
||
|
|
; CHECK: liveins: $vgpr0
|
||
|
|
; CHECK: %arg:_(s32) = COPY $vgpr0
|
||
|
|
; CHECK: %shiftamt:_(s32) = G_CONSTANT i32 16
|
||
|
|
; CHECK: %shift:_(s32) = G_SHL %arg, %shiftamt(s32)
|
||
|
|
; CHECK: %result:_(s32) = G_AMDGPU_CVT_F32_UBYTE2 %shift
|
||
|
|
; CHECK: $vgpr0 = COPY %result(s32)
|
||
|
|
%arg:_(s32) = COPY $vgpr0
|
||
|
|
%shiftamt:_(s32) = G_CONSTANT i32 16
|
||
|
|
%shift:_(s32) = G_SHL %arg, %shiftamt
|
||
|
|
%result:_(s32) = G_AMDGPU_CVT_F32_UBYTE2 %shift
|
||
|
|
$vgpr0 = COPY %result
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: cvt_f32_ubyte3_shl_16
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $vgpr0
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: cvt_f32_ubyte3_shl_16
|
||
|
|
; CHECK: liveins: $vgpr0
|
||
|
|
; CHECK: %arg:_(s32) = COPY $vgpr0
|
||
|
|
; CHECK: %result:_(s32) = G_AMDGPU_CVT_F32_UBYTE1 %arg
|
||
|
|
; CHECK: $vgpr0 = COPY %result(s32)
|
||
|
|
%arg:_(s32) = COPY $vgpr0
|
||
|
|
%shiftamt:_(s32) = G_CONSTANT i32 16
|
||
|
|
%shift:_(s32) = G_SHL %arg, %shiftamt
|
||
|
|
%result:_(s32) = G_AMDGPU_CVT_F32_UBYTE3 %shift
|
||
|
|
$vgpr0 = COPY %result
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: cvt_f32_ubyte0_shl_24
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $vgpr0
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: cvt_f32_ubyte0_shl_24
|
||
|
|
; CHECK: liveins: $vgpr0
|
||
|
|
; CHECK: %arg:_(s32) = COPY $vgpr0
|
||
|
|
; CHECK: %shiftamt:_(s32) = G_CONSTANT i32 24
|
||
|
|
; CHECK: %shift:_(s32) = G_SHL %arg, %shiftamt(s32)
|
||
|
|
; CHECK: %result:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 %shift
|
||
|
|
; CHECK: $vgpr0 = COPY %result(s32)
|
||
|
|
%arg:_(s32) = COPY $vgpr0
|
||
|
|
%shiftamt:_(s32) = G_CONSTANT i32 24
|
||
|
|
%shift:_(s32) = G_SHL %arg, %shiftamt
|
||
|
|
%result:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 %shift
|
||
|
|
$vgpr0 = COPY %result
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: cvt_f32_ubyte1_shl_24
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $vgpr0
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: cvt_f32_ubyte1_shl_24
|
||
|
|
; CHECK: liveins: $vgpr0
|
||
|
|
; CHECK: %arg:_(s32) = COPY $vgpr0
|
||
|
|
; CHECK: %shiftamt:_(s32) = G_CONSTANT i32 24
|
||
|
|
; CHECK: %shift:_(s32) = G_SHL %arg, %shiftamt(s32)
|
||
|
|
; CHECK: %result:_(s32) = G_AMDGPU_CVT_F32_UBYTE1 %shift
|
||
|
|
; CHECK: $vgpr0 = COPY %result(s32)
|
||
|
|
%arg:_(s32) = COPY $vgpr0
|
||
|
|
%shiftamt:_(s32) = G_CONSTANT i32 24
|
||
|
|
%shift:_(s32) = G_SHL %arg, %shiftamt
|
||
|
|
%result:_(s32) = G_AMDGPU_CVT_F32_UBYTE1 %shift
|
||
|
|
$vgpr0 = COPY %result
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: cvt_f32_ubyte2_shl_24
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $vgpr0
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: cvt_f32_ubyte2_shl_24
|
||
|
|
; CHECK: liveins: $vgpr0
|
||
|
|
; CHECK: %arg:_(s32) = COPY $vgpr0
|
||
|
|
; CHECK: %shiftamt:_(s32) = G_CONSTANT i32 24
|
||
|
|
; CHECK: %shift:_(s32) = G_SHL %arg, %shiftamt(s32)
|
||
|
|
; CHECK: %result:_(s32) = G_AMDGPU_CVT_F32_UBYTE2 %shift
|
||
|
|
; CHECK: $vgpr0 = COPY %result(s32)
|
||
|
|
%arg:_(s32) = COPY $vgpr0
|
||
|
|
%shiftamt:_(s32) = G_CONSTANT i32 24
|
||
|
|
%shift:_(s32) = G_SHL %arg, %shiftamt
|
||
|
|
%result:_(s32) = G_AMDGPU_CVT_F32_UBYTE2 %shift
|
||
|
|
$vgpr0 = COPY %result
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: cvt_f32_ubyte3_shl_24
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $vgpr0
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: cvt_f32_ubyte3_shl_24
|
||
|
|
; CHECK: liveins: $vgpr0
|
||
|
|
; CHECK: %arg:_(s32) = COPY $vgpr0
|
||
|
|
; CHECK: %shiftamt:_(s32) = G_CONSTANT i32 24
|
||
|
|
; CHECK: %shift:_(s32) = G_SHL %arg, %shiftamt(s32)
|
||
|
|
; CHECK: %result:_(s32) = G_AMDGPU_CVT_F32_UBYTE3 %shift
|
||
|
|
; CHECK: $vgpr0 = COPY %result(s32)
|
||
|
|
%arg:_(s32) = COPY $vgpr0
|
||
|
|
%shiftamt:_(s32) = G_CONSTANT i32 24
|
||
|
|
%shift:_(s32) = G_SHL %arg, %shiftamt
|
||
|
|
%result:_(s32) = G_AMDGPU_CVT_F32_UBYTE3 %shift
|
||
|
|
$vgpr0 = COPY %result
|
||
|
|
...
|
||
|
|
|
||
|
|
# Shift amount is wrong
|
||
|
|
---
|
||
|
|
name: cvt_f32_ubyte1_shl_7
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $vgpr0
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: cvt_f32_ubyte1_shl_7
|
||
|
|
; CHECK: liveins: $vgpr0
|
||
|
|
; CHECK: %arg:_(s32) = COPY $vgpr0
|
||
|
|
; CHECK: %shiftamt:_(s32) = G_CONSTANT i32 7
|
||
|
|
; CHECK: %shift:_(s32) = G_SHL %arg, %shiftamt(s32)
|
||
|
|
; CHECK: %result:_(s32) = G_AMDGPU_CVT_F32_UBYTE1 %shift
|
||
|
|
; CHECK: $vgpr0 = COPY %result(s32)
|
||
|
|
%arg:_(s32) = COPY $vgpr0
|
||
|
|
%shiftamt:_(s32) = G_CONSTANT i32 7
|
||
|
|
%shift:_(s32) = G_SHL %arg, %shiftamt
|
||
|
|
%result:_(s32) = G_AMDGPU_CVT_F32_UBYTE1 %shift
|
||
|
|
$vgpr0 = COPY %result
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: cvt_f32_ubyte3_shl_17
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $vgpr0
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: cvt_f32_ubyte3_shl_17
|
||
|
|
; CHECK: liveins: $vgpr0
|
||
|
|
; CHECK: %arg:_(s32) = COPY $vgpr0
|
||
|
|
; CHECK: %shiftamt:_(s32) = G_CONSTANT i32 17
|
||
|
|
; CHECK: %shift:_(s32) = G_SHL %arg, %shiftamt(s32)
|
||
|
|
; CHECK: %result:_(s32) = G_AMDGPU_CVT_F32_UBYTE3 %shift
|
||
|
|
; CHECK: $vgpr0 = COPY %result(s32)
|
||
|
|
%arg:_(s32) = COPY $vgpr0
|
||
|
|
%shiftamt:_(s32) = G_CONSTANT i32 17
|
||
|
|
%shift:_(s32) = G_SHL %arg, %shiftamt
|
||
|
|
%result:_(s32) = G_AMDGPU_CVT_F32_UBYTE3 %shift
|
||
|
|
$vgpr0 = COPY %result
|
||
|
|
...
|