You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
99 lines
3.8 KiB
99 lines
3.8 KiB
4 months ago
|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||
|
|
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
|
||
|
|
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
|
||
|
|
|
||
|
|
---
|
||
|
|
name: writelane_sss
|
||
|
|
legalized: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $sgpr0, $sgpr1, $sgpr2
|
||
|
|
; CHECK-LABEL: name: writelane_sss
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||
|
|
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||
|
|
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
||
|
|
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
|
||
|
|
; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.writelane), [[COPY]](s32), [[COPY1]](s32), [[COPY3]](s32)
|
||
|
|
%0:_(s32) = COPY $sgpr0
|
||
|
|
%1:_(s32) = COPY $sgpr1
|
||
|
|
%2:_(s32) = COPY $sgpr2
|
||
|
|
%3:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.writelane), %0, %1, %2
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: writelane_ssv
|
||
|
|
legalized: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $sgpr0, $sgpr1, $vgpr0
|
||
|
|
; CHECK-LABEL: name: writelane_ssv
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||
|
|
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
||
|
|
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||
|
|
; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.writelane), [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
|
||
|
|
%0:_(s32) = COPY $sgpr0
|
||
|
|
%1:_(s32) = COPY $sgpr1
|
||
|
|
%2:_(s32) = COPY $vgpr0
|
||
|
|
%3:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.writelane), %0, %1, %2
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: writelane_vsv
|
||
|
|
legalized: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $sgpr0, $vgpr0, $vgpr1
|
||
|
|
; CHECK-LABEL: name: writelane_vsv
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
|
||
|
|
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||
|
|
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||
|
|
; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY]](s32), implicit $exec
|
||
|
|
; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.writelane), [[V_READFIRSTLANE_B32_]](s32), [[COPY1]](s32), [[COPY2]](s32)
|
||
|
|
%0:_(s32) = COPY $vgpr0
|
||
|
|
%1:_(s32) = COPY $sgpr0
|
||
|
|
%2:_(s32) = COPY $vgpr1
|
||
|
|
%3:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.writelane), %0, %1, %2
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: writelane_vvv
|
||
|
|
legalized: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $vgpr0, $vgpr1
|
||
|
|
; CHECK-LABEL: name: writelane_vvv
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
|
||
|
|
; CHECK: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
|
||
|
|
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
|
||
|
|
; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY]](s32), implicit $exec
|
||
|
|
; CHECK: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY1]](s32), implicit $exec
|
||
|
|
; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.writelane), [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[COPY2]](s32)
|
||
|
|
%0:_(s32) = COPY $vgpr0
|
||
|
|
%1:_(s32) = COPY $vgpr1
|
||
|
|
%2:_(s32) = COPY $vgpr2
|
||
|
|
%3:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.writelane), %0, %1, %2
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: writelane_svv
|
||
|
|
legalized: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $sgpr0, $vgpr0, $vgpr1
|
||
|
|
; CHECK-LABEL: name: writelane_svv
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||
|
|
; CHECK: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
|
||
|
|
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||
|
|
; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY1]](s32), implicit $exec
|
||
|
|
; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.writelane), [[COPY]](s32), [[V_READFIRSTLANE_B32_]](s32), [[COPY2]](s32)
|
||
|
|
%0:_(s32) = COPY $sgpr0
|
||
|
|
%1:_(s32) = COPY $vgpr0
|
||
|
|
%2:_(s32) = COPY $vgpr1
|
||
|
|
%3:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.writelane), %0, %1, %2
|
||
|
|
...
|