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55 lines
1.7 KiB
55 lines
1.7 KiB
4 months ago
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; optnone disables AMDGPUAnnotateUniformValues, so no branch is known
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; to be uniform during instruction selection. The custom selection for
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; brcond was not checking if the branch was uniform, relying on the
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; selection pattern to check that. That would fail, so then the branch
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; would fail to select.
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; GCN-LABEL: {{^}}copytoreg_divergent_brcond:
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; GCN: s_branch
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; GCN-DAG: v_cmp_lt_i32
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; GCN-DAG: v_cmp_gt_i32
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; GCN: s_and_b64
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; GCN: s_mov_b64 exec
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; GCN: s_or_b64 exec, exec
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; GCN: {{[s|v]}}_cmp_eq_u32
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; GCN: s_cbranch
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; GCN-NEXT: s_branch
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define amdgpu_kernel void @copytoreg_divergent_brcond(i32 %arg, i32 %arg1, i32 %arg2) #0 {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp3 = zext i32 %tmp to i64
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%tmp5 = add i64 %tmp3, undef
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%tmp6 = trunc i64 %tmp5 to i32
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%tmp7 = mul nsw i32 %tmp6, %arg2
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br label %bb8
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bb8.loopexit: ; preds = %bb14
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br label %bb8
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bb8: ; preds = %bb8.loopexit, %bb
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br label %bb9
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bb9: ; preds = %bb14, %bb8
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%tmp10 = icmp slt i32 %tmp7, %arg1
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%tmp11 = icmp sgt i32 %arg, 0
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%tmp12 = and i1 %tmp10, %tmp11
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br i1 %tmp12, label %bb13, label %bb14
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bb13: ; preds = %bb9
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store volatile i32 0, i32 addrspace(1)* undef, align 4
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br label %bb14
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bb14: ; preds = %bb13, %bb9
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%tmp15 = icmp eq i32 %arg2, 1
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br i1 %tmp15, label %bb8.loopexit, label %bb9
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #0 = { nounwind optnone noinline }
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attributes #1 = { nounwind readnone speculatable }
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