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65 lines
3.0 KiB
65 lines
3.0 KiB
4 months ago
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1030 < %s | FileCheck -check-prefixes=GCN,GFX10 %s
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; --------------------------------------------------------------------------------
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; amdgcn atomic csub
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; --------------------------------------------------------------------------------
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define amdgpu_ps float @global_csub_saddr_i32_rtn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
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; GCN-LABEL: global_csub_saddr_i32_rtn:
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; GCN: ; %bb.0:
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; GCN-NEXT: global_atomic_csub v0, v0, v1, s[2:3] glc
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: ; return to shader part epilog
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%zext.offset = zext i32 %voffset to i64
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%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
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%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i32 addrspace(1)*
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%rtn = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %cast.gep0, i32 %data)
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%cast.rtn = bitcast i32 %rtn to float
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ret float %cast.rtn
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}
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define amdgpu_ps float @global_csub_saddr_i32_rtn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
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; GCN-LABEL: global_csub_saddr_i32_rtn_neg128:
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; GCN: ; %bb.0:
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; GCN-NEXT: global_atomic_csub v0, v0, v1, s[2:3] offset:-128 glc
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: ; return to shader part epilog
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%zext.offset = zext i32 %voffset to i64
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%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
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%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
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%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)*
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%rtn = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %cast.gep1, i32 %data)
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%cast.rtn = bitcast i32 %rtn to float
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ret float %cast.rtn
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}
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define amdgpu_ps void @global_csub_saddr_i32_nortn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
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; GCN-LABEL: global_csub_saddr_i32_nortn:
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; GCN: ; %bb.0:
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; GCN-NEXT: global_atomic_csub v0, v0, v1, s[2:3] glc
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; GCN-NEXT: s_endpgm
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%zext.offset = zext i32 %voffset to i64
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%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
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%cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i32 addrspace(1)*
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%unused = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %cast.gep0, i32 %data)
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ret void
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}
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define amdgpu_ps void @global_csub_saddr_i32_nortn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) {
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; GCN-LABEL: global_csub_saddr_i32_nortn_neg128:
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; GCN: ; %bb.0:
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; GCN-NEXT: global_atomic_csub v0, v0, v1, s[2:3] offset:-128 glc
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; GCN-NEXT: s_endpgm
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%zext.offset = zext i32 %voffset to i64
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%gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
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%gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128
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%cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)*
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%unused = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %cast.gep1, i32 %data)
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ret void
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}
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declare i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* nocapture, i32) #0
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attributes #0 = { argmemonly nounwind willreturn }
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