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100 lines
3.6 KiB
100 lines
3.6 KiB
4 months ago
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; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck %s
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;
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; This test checks that the lds input queue will is empty at the end of
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; the ALU clause.
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; CHECK-LABEL: {{^}}lds_input_queue:
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; CHECK: LDS_READ_RET * OQAP
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; CHECK-NOT: ALU clause
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; CHECK: MOV * T{{[0-9]\.[XYZW]}}, OQAP
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@local_mem = internal unnamed_addr addrspace(3) global [2 x i32] undef, align 4
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define amdgpu_kernel void @lds_input_queue(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %index) {
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entry:
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%0 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(3)* @local_mem, i32 0, i32 %index
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%1 = load i32, i32 addrspace(3)* %0
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call void @llvm.r600.group.barrier()
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; This will start a new clause for the vertex fetch
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%2 = load i32, i32 addrspace(1)* %in
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%3 = add i32 %1, %2
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store i32 %3, i32 addrspace(1)* %out
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ret void
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}
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declare void @llvm.r600.group.barrier() nounwind convergent
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; The machine scheduler does not do proper alias analysis and assumes that
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; loads from global values (Note that a global value is different that a
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; value from global memory. A global value is a value that is declared
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; outside of a function, it can reside in any address space) alias with
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; all other loads.
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;
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; This is a problem for scheduling the reads from the local data share (lds).
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; These reads are implemented using two instructions. The first copies the
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; data from lds into the lds output queue, and the second moves the data from
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; the input queue into main memory. These two instructions don't have to be
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; scheduled one after the other, but they do need to be scheduled in the same
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; clause. The aliasing problem mentioned above causes problems when there is a
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; load from global memory which immediately follows a load from a global value that
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; has been declared in the local memory space:
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;
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; %0 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(3)* @local_mem, i32 0, i32 %index
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; %1 = load i32, i32 addrspace(3)* %0
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; %2 = load i32, i32 addrspace(1)* %in
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;
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; The instruction selection phase will generate ISA that looks like this:
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; %oqap = LDS_READ_RET
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; %0 = MOV %oqap
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; %1 = VTX_READ_32
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; %2 = ADD_INT %1, %0
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;
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; The bottom scheduler will schedule the two ALU instructions first:
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;
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; UNSCHEDULED:
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; %oqap = LDS_READ_RET
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; %1 = VTX_READ_32
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;
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; SCHEDULED:
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;
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; %0 = MOV %oqap
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; %2 = ADD_INT %1, %2
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;
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; The lack of proper aliasing results in the local memory read (LDS_READ_RET)
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; to consider the global memory read (VTX_READ_32) has a chain dependency, so
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; the global memory read will always be scheduled first. This will give us a
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; final program which looks like this:
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;
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; Alu clause:
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; %oqap = LDS_READ_RET
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; VTX clause:
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; %1 = VTX_READ_32
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; Alu clause:
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; %0 = MOV %oqap
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; %2 = ADD_INT %1, %2
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;
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; This is an illegal program because the oqap def and use know occur in
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; different ALU clauses.
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;
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; This test checks this scenario and makes sure it doesn't result in an
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; illegal program. For now, we have fixed this issue by merging the
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; LDS_READ_RET and MOV together during instruction selection and then
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; expanding them after scheduling. Once the scheduler has better alias
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; analysis, we should be able to keep these instructions sparate before
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; scheduling.
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;
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; CHECK-LABEL: {{^}}local_global_alias:
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; CHECK: LDS_READ_RET
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; CHECK-NOT: ALU clause
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; CHECK: MOV * T{{[0-9]\.[XYZW]}}, OQAP
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define amdgpu_kernel void @local_global_alias(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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entry:
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%0 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(3)* @local_mem, i32 0, i32 0
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%1 = load i32, i32 addrspace(3)* %0
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%2 = load i32, i32 addrspace(1)* %in
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%3 = add i32 %2, %1
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store i32 %3, i32 addrspace(1)* %out
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ret void
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}
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