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35 lines
1.2 KiB
35 lines
1.2 KiB
4 months ago
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; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs <%s | FileCheck -check-prefixes=GCN %s
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;
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; This test checks that we have the correct fold for zext(cc1) - zext(cc2).
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;
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; GCN-LABEL: sub_zext_zext:
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; GCN: ds_read_b32 [[VAL:v[0-9]+]],
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; GCN: v_cmp_lt_f32{{.*}} vcc, 0, [[VAL]]
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; GCN: v_cndmask_{{.*}} [[ZEXTCC1:v[0-9]+]], 0, 1, vcc
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; GCN: v_cmp_gt_f32{{.*}} vcc, 0, [[VAL]]
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; GCN: v_subbrev{{.*}} {{v[0-9]+}}, vcc, 0, [[ZEXTCC1]], vcc
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;
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; Before the reversion that this test is attached to, the compiler commuted
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; the operands to the sub and used different logic to select the addc/subc
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; instruction:
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; sub zext (setcc), x => addcarry 0, x, setcc
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; sub sext (setcc), x => subcarry 0, x, setcc
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;
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; ... but that is bogus. I believe it is not possible to fold those commuted
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; patterns into any form of addcarry or subcarry.
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define amdgpu_cs float @sub_zext_zext() {
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.entry:
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%t519 = load float, float addrspace(3)* null
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%t524 = fcmp ogt float %t519, 0.000000e+00
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%t525 = fcmp olt float %t519, 0.000000e+00
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%t526 = zext i1 %t524 to i32
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%t527 = zext i1 %t525 to i32
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%t528 = sub nsw i32 %t526, %t527
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%t529 = sitofp i32 %t528 to float
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ret float %t529
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}
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