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v811_spc009/external/llvm-project/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-exts.mir

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v811_spc009_project
4 months ago
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- |
define void @test_trunc_and_zext_s1_to_s32() { ret void }
define void @test_trunc_and_sext_s1_to_s32() { ret void }
define void @test_trunc_and_anyext_s1_to_s32() { ret void }
define void @test_trunc_and_zext_s8_to_s32() { ret void }
define void @test_trunc_and_sext_s8_to_s32() { ret void }
define void @test_trunc_and_anyext_s8_to_s32() { ret void }
define void @test_trunc_and_zext_s16_to_s32() { ret void }
define void @test_trunc_and_sext_s16_to_s32() { ret void }
define void @test_trunc_and_anyext_s16_to_s32() { ret void }
define void @test_trunc_and_zext_s1_to_s16() { ret void }
define void @test_trunc_and_sext_s1_to_s16() { ret void }
define void @test_trunc_and_anyext_s1_to_s16() { ret void }
define void @test_trunc_and_zext_s8_to_s16() { ret void }
define void @test_trunc_and_sext_s8_to_s16() { ret void }
define void @test_trunc_and_anyext_s8_to_s16() { ret void }
define void @test_trunc_and_zext_s1_to_s8() { ret void }
define void @test_trunc_and_sext_s1_to_s8() { ret void }
define void @test_trunc_and_anyext_s1_to_s8() { ret void }
...
---
name: test_trunc_and_zext_s1_to_s32
legalized: true
regBankSelected: true
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
body: |
bb.0:
liveins: $r0
; CHECK-LABEL: name: test_trunc_and_zext_s1_to_s32
; CHECK: liveins: $r0
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY [[COPY]]
; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY1]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2ANDri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s1) = G_TRUNC %0(s32)
%2(s32) = G_ZEXT %1(s1)
$r0 = COPY %2(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_trunc_and_sext_s1_to_s32
legalized: true
regBankSelected: true
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
body: |
bb.0:
liveins: $r0
; CHECK-LABEL: name: test_trunc_and_sext_s1_to_s32
; CHECK: liveins: $r0
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY [[COPY]]
; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY1]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[t2RSBri:%[0-9]+]]:rgpr = t2RSBri [[t2ANDri]], 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2RSBri]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s1) = G_TRUNC %0(s32)
%2(s32) = G_SEXT %1(s1)
$r0 = COPY %2(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_trunc_and_anyext_s1_to_s32
legalized: true
regBankSelected: true
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
body: |
bb.0:
liveins: $r0
; CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s32
; CHECK: liveins: $r0
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: $r0 = COPY [[COPY]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s1) = G_TRUNC %0(s32)
%2(s32) = G_ANYEXT %1(s1)
$r0 = COPY %2(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_trunc_and_zext_s8_to_s32
legalized: true
regBankSelected: true
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
body: |
bb.0:
liveins: $r0
; CHECK-LABEL: name: test_trunc_and_zext_s8_to_s32
; CHECK: liveins: $r0
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY [[COPY]]
; CHECK: [[t2UXTB:%[0-9]+]]:rgpr = t2UXTB [[COPY1]], 0, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY [[t2UXTB]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s8) = G_TRUNC %0(s32)
%2(s32) = G_ZEXT %1(s8)
$r0 = COPY %2(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_trunc_and_sext_s8_to_s32
legalized: true
regBankSelected: true
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
body: |
bb.0:
liveins: $r0
; CHECK-LABEL: name: test_trunc_and_sext_s8_to_s32
; CHECK: liveins: $r0
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY [[COPY]]
; CHECK: [[t2SXTB:%[0-9]+]]:rgpr = t2SXTB [[COPY1]], 0, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY [[t2SXTB]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s8) = G_TRUNC %0(s32)
%2(s32) = G_SEXT %1(s8)
$r0 = COPY %2(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_trunc_and_anyext_s8_to_s32
legalized: true
regBankSelected: true
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
body: |
bb.0:
liveins: $r0
; CHECK-LABEL: name: test_trunc_and_anyext_s8_to_s32
; CHECK: liveins: $r0
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: $r0 = COPY [[COPY]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s8) = G_TRUNC %0(s32)
%2(s32) = G_ANYEXT %1(s8)
$r0 = COPY %2(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_trunc_and_zext_s16_to_s32
legalized: true
regBankSelected: true
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
body: |
bb.0:
liveins: $r0
; CHECK-LABEL: name: test_trunc_and_zext_s16_to_s32
; CHECK: liveins: $r0
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY [[COPY]]
; CHECK: [[t2UXTH:%[0-9]+]]:rgpr = t2UXTH [[COPY1]], 0, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY [[t2UXTH]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s16) = G_TRUNC %0(s32)
%2(s32) = G_ZEXT %1(s16)
$r0 = COPY %2(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_trunc_and_sext_s16_to_s32
legalized: true
regBankSelected: true
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
body: |
bb.0:
liveins: $r0
; CHECK-LABEL: name: test_trunc_and_sext_s16_to_s32
; CHECK: liveins: $r0
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY [[COPY]]
; CHECK: [[t2SXTH:%[0-9]+]]:rgpr = t2SXTH [[COPY1]], 0, 14 /* CC::al */, $noreg
; CHECK: $r0 = COPY [[t2SXTH]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s16) = G_TRUNC %0(s32)
%2(s32) = G_SEXT %1(s16)
$r0 = COPY %2(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_trunc_and_anyext_s16_to_s32
legalized: true
regBankSelected: true
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
body: |
bb.0:
liveins: $r0
; CHECK-LABEL: name: test_trunc_and_anyext_s16_to_s32
; CHECK: liveins: $r0
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: $r0 = COPY [[COPY]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s16) = G_TRUNC %0(s32)
%2(s32) = G_ANYEXT %1(s16)
$r0 = COPY %2(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_trunc_and_zext_s1_to_s16
legalized: true
regBankSelected: true
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
body: |
bb.0:
liveins: $r0, $r1
; CHECK-LABEL: name: test_trunc_and_zext_s1_to_s16
; CHECK: liveins: $r0, $r1
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]]
; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY2]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2STRHi12 [[t2ANDri]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store 2)
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
%1(s32) = COPY $r1
%2(s1) = G_TRUNC %1(s32)
%3(s16) = G_ZEXT %2(s1)
G_STORE %3(s16), %0(p0) :: (store 2)
BX_RET 14, $noreg
...
---
name: test_trunc_and_sext_s1_to_s16
legalized: true
regBankSelected: true
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
body: |
bb.0:
liveins: $r0, $r1
; CHECK-LABEL: name: test_trunc_and_sext_s1_to_s16
; CHECK: liveins: $r0, $r1
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]]
; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY2]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[t2RSBri:%[0-9]+]]:rgpr = t2RSBri [[t2ANDri]], 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2STRHi12 [[t2RSBri]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store 2)
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
%1(s32) = COPY $r1
%2(s1) = G_TRUNC %1(s32)
%3(s16) = G_SEXT %2(s1)
G_STORE %3(s16), %0(p0) :: (store 2)
BX_RET 14, $noreg
...
---
name: test_trunc_and_anyext_s1_to_s16
legalized: true
regBankSelected: true
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
body: |
bb.0:
liveins: $r0, $r1
; CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s16
; CHECK: liveins: $r0, $r1
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]]
; CHECK: t2STRHi12 [[COPY2]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store 2)
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
%1(s32) = COPY $r1
%2(s1) = G_TRUNC %1(s32)
%3(s16) = G_ANYEXT %2(s1)
G_STORE %3(s16), %0(p0) :: (store 2)
BX_RET 14, $noreg
...
---
name: test_trunc_and_zext_s8_to_s16
legalized: true
regBankSelected: true
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
body: |
bb.0:
liveins: $r0, $r1
; CHECK-LABEL: name: test_trunc_and_zext_s8_to_s16
; CHECK: liveins: $r0, $r1
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]]
; CHECK: [[t2UXTB:%[0-9]+]]:rgpr = t2UXTB [[COPY2]], 0, 14 /* CC::al */, $noreg
; CHECK: t2STRHi12 [[t2UXTB]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store 2)
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
%1(s32) = COPY $r1
%2(s8) = G_TRUNC %1(s32)
%3(s16) = G_ZEXT %2(s8)
G_STORE %3(s16), %0(p0) :: (store 2)
BX_RET 14, $noreg
...
---
name: test_trunc_and_sext_s8_to_s16
legalized: true
regBankSelected: true
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
body: |
bb.0:
liveins: $r0, $r1
; CHECK-LABEL: name: test_trunc_and_sext_s8_to_s16
; CHECK: liveins: $r0, $r1
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]]
; CHECK: [[t2SXTB:%[0-9]+]]:rgpr = t2SXTB [[COPY2]], 0, 14 /* CC::al */, $noreg
; CHECK: t2STRHi12 [[t2SXTB]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store 2)
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
%1(s32) = COPY $r1
%2(s8) = G_TRUNC %1(s32)
%3(s16) = G_SEXT %2(s8)
G_STORE %3(s16), %0(p0) :: (store 2)
BX_RET 14, $noreg
...
---
name: test_trunc_and_anyext_s8_to_s16
legalized: true
regBankSelected: true
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
body: |
bb.0:
liveins: $r0, $r1
; CHECK-LABEL: name: test_trunc_and_anyext_s8_to_s16
; CHECK: liveins: $r0, $r1
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]]
; CHECK: t2STRHi12 [[COPY2]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store 2)
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
%1(s32) = COPY $r1
%2(s8) = G_TRUNC %1(s32)
%3(s16) = G_ANYEXT %2(s8)
G_STORE %3(s16), %0(p0) :: (store 2)
BX_RET 14, $noreg
...
---
name: test_trunc_and_zext_s1_to_s8
legalized: true
regBankSelected: true
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
body: |
bb.0:
liveins: $r0, $r1
; CHECK-LABEL: name: test_trunc_and_zext_s1_to_s8
; CHECK: liveins: $r0, $r1
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]]
; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY2]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2STRBi12 [[t2ANDri]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store 1)
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
%1(s32) = COPY $r1
%2(s1) = G_TRUNC %1(s32)
%3(s8) = G_ZEXT %2(s1)
G_STORE %3(s8), %0(p0) :: (store 1)
BX_RET 14, $noreg
...
---
name: test_trunc_and_sext_s1_to_s8
legalized: true
regBankSelected: true
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
body: |
bb.0:
liveins: $r0, $r1
; CHECK-LABEL: name: test_trunc_and_sext_s1_to_s8
; CHECK: liveins: $r0, $r1
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]]
; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY2]], 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[t2RSBri:%[0-9]+]]:rgpr = t2RSBri [[t2ANDri]], 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2STRBi12 [[t2RSBri]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store 1)
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
%1(s32) = COPY $r1
%2(s1) = G_TRUNC %1(s32)
%3(s8) = G_SEXT %2(s1)
G_STORE %3(s8), %0(p0) :: (store 1)
BX_RET 14, $noreg
...
---
name: test_trunc_and_anyext_s1_to_s8
legalized: true
regBankSelected: true
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
body: |
bb.0:
liveins: $r0, $r1
; CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s8
; CHECK: liveins: $r0, $r1
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]]
; CHECK: t2STRBi12 [[COPY2]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store 1)
; CHECK: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
%1(s32) = COPY $r1
%2(s1) = G_TRUNC %1(s32)
%3(s8) = G_ANYEXT %2(s1)
G_STORE %3(s8), %0(p0) :: (store 1)
BX_RET 14, $noreg
...