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104 lines
2.8 KiB
104 lines
2.8 KiB
4 months ago
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# RUN: llc -run-pass=peephole-opt %s -o - | FileCheck %s
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# Here we check that the peephole cmp rewrite is not triggered, because
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# there is store instruction between the tMUL and tCMP, i.e. there are
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# no constants to reorder.
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--- |
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; ModuleID = 'cmp2-peephole-thumb.ll'
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source_filename = "<stdin>"
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumb-none--eabi"
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define i32 @g(i32 %a, i32 %b) {
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entry:
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%retval = alloca i32, align 4
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%mul = alloca i32, align 4
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%mul1 = mul nsw i32 %a, %b
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store i32 %mul1, i32* %mul, align 4
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%0 = load i32, i32* %mul, align 4
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%cmp = icmp sle i32 %0, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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store i32 42, i32* %retval, align 4
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br label %return
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if.end: ; preds = %entry
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store i32 1, i32* %retval, align 4
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br label %return
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return: ; preds = %if.end, %if.then
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%1 = load i32, i32* %retval, align 4
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ret i32 %1
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}
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...
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---
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name: g
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# CHECK-LABEL: name: g
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alignment: 2
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: tgpr }
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- { id: 1, class: tgpr }
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- { id: 2, class: tgpr }
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- { id: 3, class: tgpr }
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- { id: 4, class: tgpr }
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- { id: 5, class: tgpr }
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liveins:
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- { reg: '$r0', virtual-reg: '%0' }
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- { reg: '$r1', virtual-reg: '%1' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 4
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adjustsStack: false
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hasCalls: false
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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stack:
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- { id: 0, name: retval, offset: 0, size: 4, alignment: 4, local-offset: -4 }
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- { id: 1, name: mul, offset: 0, size: 4, alignment: 4, local-offset: -8 }
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# CHECK: tMUL
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# CHECK-NEXT: tSTRspi
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# CHECK-NEXT: tCMPi8
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body: |
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bb.0.entry:
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liveins: $r0, $r1
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%1 = COPY $r1
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%0 = COPY $r0
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%2, $cpsr = tMUL %0, %1, 14, $noreg
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tSTRspi %2, %stack.1.mul, 0, 14, $noreg :: (store 4 into %ir.mul)
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tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
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tBcc %bb.2.if.end, 12, $cpsr
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tB %bb.1.if.then, 14, $noreg
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bb.1.if.then:
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%4, $cpsr = tMOVi8 42, 14, $noreg
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tSTRspi killed %4, %stack.0.retval, 0, 14, $noreg :: (store 4 into %ir.retval)
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tB %bb.3.return, 14, $noreg
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bb.2.if.end:
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%3, $cpsr = tMOVi8 1, 14, $noreg
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tSTRspi killed %3, %stack.0.retval, 0, 14, $noreg :: (store 4 into %ir.retval)
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bb.3.return:
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%5 = tLDRspi %stack.0.retval, 0, 14, $noreg :: (dereferenceable load 4 from %ir.retval)
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$r0 = COPY %5
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tBX_RET 14, $noreg, implicit $r0
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...
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