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85 lines
4.0 KiB
85 lines
4.0 KiB
4 months ago
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; XFAIL: *
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; Needs some fixed in the pipeliner.
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; RUN: llc -march=hexagon < %s -pipeliner-experimental-cg=true | FileCheck %s
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; CHECK: endloop0
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; CHECK: vmem
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; CHECK: vmem([[REG:r([0-9]+)]]+#1) =
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; CHECK: vmem([[REG]]+#0) =
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define void @f0(i32 %a0) local_unnamed_addr #0 {
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b0:
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br label %b1
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b1: ; preds = %b1, %b0
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%v0 = phi i32 [ %v33, %b1 ], [ %a0, %b0 ]
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%v1 = phi <16 x i32>* [ %v32, %b1 ], [ undef, %b0 ]
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%v2 = phi <16 x i32>* [ %v23, %b1 ], [ undef, %b0 ]
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%v3 = phi <16 x i32>* [ %v10, %b1 ], [ undef, %b0 ]
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%v4 = phi <16 x i32>* [ %v8, %b1 ], [ null, %b0 ]
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%v5 = phi <32 x i32> [ %v12, %b1 ], [ undef, %b0 ]
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%v6 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v5)
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%v7 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %v6, <16 x i32> undef, i32 6)
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%v8 = getelementptr inbounds <16 x i32>, <16 x i32>* %v4, i32 1
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%v9 = load <16 x i32>, <16 x i32>* %v4, align 64
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%v10 = getelementptr inbounds <16 x i32>, <16 x i32>* %v3, i32 1
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%v11 = load <16 x i32>, <16 x i32>* %v3, align 64
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%v12 = tail call <32 x i32> @llvm.hexagon.V6.vsububh(<16 x i32> %v11, <16 x i32> %v9)
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%v13 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v12)
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%v14 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v13, <16 x i32> undef)
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%v15 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %v14, <16 x i32> undef, i32 4)
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%v16 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v14, <16 x i32> %v15)
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%v17 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v14, <16 x i32> undef, i32 4)
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%v18 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v16, <16 x i32> undef, i32 2)
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%v19 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> undef, <16 x i32> %v17)
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%v20 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v18, <16 x i32> %v19)
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%v21 = getelementptr inbounds <16 x i32>, <16 x i32>* %v2, i32 1
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%v22 = load <16 x i32>, <16 x i32>* %v2, align 64
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%v23 = getelementptr inbounds <16 x i32>, <16 x i32>* %v2, i32 2
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%v24 = load <16 x i32>, <16 x i32>* %v21, align 64
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%v25 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v22, <16 x i32> %v7)
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%v26 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v24, <16 x i32> undef)
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%v27 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v25, <16 x i32> %v20)
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%v28 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v26, <16 x i32> %v20)
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store <16 x i32> %v27, <16 x i32>* %v2, align 64
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store <16 x i32> %v28, <16 x i32>* %v21, align 64
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%v29 = tail call <16 x i32> @llvm.hexagon.V6.vmpyhsrs(<16 x i32> %v27, i32 17760527)
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%v30 = tail call <16 x i32> @llvm.hexagon.V6.vmpyhsrs(<16 x i32> %v28, i32 17760527)
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%v31 = tail call <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32> %v30, <16 x i32> %v29)
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%v32 = getelementptr inbounds <16 x i32>, <16 x i32>* %v1, i32 1
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store <16 x i32> %v31, <16 x i32>* %v1, align 64
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%v33 = add nsw i32 %v0, -64
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%v34 = icmp sgt i32 %v0, 192
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br i1 %v34, label %b1, label %b2
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b2: ; preds = %b1
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unreachable
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}
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.vsububh(<16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32>, <16 x i32>, i32) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vmpyhsrs(<16 x i32>, i32) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32>, <16 x i32>) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv65" "target-features"="+hvxv65,+hvx-length64b" }
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attributes #1 = { nounwind readnone }
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