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56 lines
1.7 KiB
56 lines
1.7 KiB
4 months ago
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; RUN: llc -march=hexagon -enable-pipeliner < %s
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; REQUIRES: asserts
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; Test that we include all the nodes in the final node ordering
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; computation. This test creates two set of nodes that are processed
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; by computeNodeOrder().
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; Function Attrs: nounwind
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define void @f0(i32 %a0) #0 {
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b0:
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%v0 = add nsw i32 undef, 4
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%v1 = ashr i32 %a0, 1
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br label %b1
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b1: ; preds = %b1, %b0
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%v2 = phi i64 [ %v5, %b1 ], [ 0, %b0 ]
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%v3 = phi i64 [ %v9, %b1 ], [ undef, %b0 ]
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%v4 = phi i32 [ %v10, %b1 ], [ 0, %b0 ]
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%v5 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 %v2, i64 %v3, i64 undef)
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%v6 = tail call i64 @llvm.hexagon.A2.combinew(i32 0, i32 0)
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%v7 = tail call i64 @llvm.hexagon.S2.shuffeh(i64 %v6, i64 undef)
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%v8 = trunc i64 %v7 to i32
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%v9 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v8, i32 undef)
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%v10 = add nsw i32 %v4, 1
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%v11 = icmp eq i32 %v10, %v1
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br i1 %v11, label %b2, label %b1
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b2: ; preds = %b1
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%v12 = trunc i64 %v5 to i32
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%v13 = inttoptr i32 %v0 to i32*
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store i32 %v12, i32* %v13, align 4, !tbaa !0
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call void @llvm.trap()
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unreachable
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}
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; Function Attrs: nounwind readnone
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declare i64 @llvm.hexagon.A2.combinew(i32, i32) #1
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; Function Attrs: nounwind readnone
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declare i64 @llvm.hexagon.M2.vdmacs.s0(i64, i64, i64) #1
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; Function Attrs: nounwind readnone
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declare i64 @llvm.hexagon.S2.shuffeh(i64, i64) #1
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; Function Attrs: noreturn nounwind
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declare void @llvm.trap() #2
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attributes #0 = { nounwind "target-cpu"="hexagonv55" }
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attributes #1 = { nounwind readnone }
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attributes #2 = { noreturn nounwind }
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!0 = !{!1, !1, i64 0}
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!1 = !{!"int", !2}
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!2 = !{!"omnipotent char", !3}
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!3 = !{!"Simple C/C++ TBAA"}
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