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71 lines
2.3 KiB
71 lines
2.3 KiB
4 months ago
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# RUN: llc -mtriple aarch64-- -run-pass instruction-select -simplify-mir \
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# RUN: -verify-machineinstrs %s -o - | FileCheck %s
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#
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# RUN: llc -mtriple aarch64-- -global-isel=true -global-isel-abort=2 \
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# RUN: -start-after=regbankselect -stop-before=finalize-isel \
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# RUN: -simplify-mir -verify-machineinstrs %s -o - 2>&1 \
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# RUN: | FileCheck %s --check-prefix=FALLBACK
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# Test that:
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# 1) MIRParser can deserialize FailedISel property.
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# 2) Machine Verifier respects FailedISel and doesn't complain needlessly.
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# 3) MIRPrinter is able to print FailedISel MIR after InstructionSelect pass.
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# 4) MIRPrinter can serialize FailedISel property.
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# 5) It's possible to start llc mid-GlobalISel pipeline from a MIR file with
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# the FailedISel property set to true and watch it properly fallback to
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# FastISel / SelectionDAG ISel.
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# 6) Resetting a MachineFunction resets unique MachineBasicBlock IDs as well.
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--- |
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64--"
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define i32 @test(i32 %a, i32 %b) #0 {
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entry:
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%add = add i32 %b, %a
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ret i32 %add
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}
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attributes #0 = { nounwind readnone ssp }
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...
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---
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# CHECK-LABEL: name: test
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# CHECK: failedISel: true
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#
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# FALLBACK: warning: Instruction selection used fallback path for test
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# FALLBACK-LABEL: name: test
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# FALLBACK-NOT: failedISel
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name: test
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alignment: 4
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legalized: true
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regBankSelected: true
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failedISel: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $w0, $w1
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; CHECK: liveins: $w0, $w1
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;
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
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; CHECK: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[COPY1]], [[COPY]]
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; CHECK: $w0 = COPY [[ADD]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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;
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; FALLBACK: body: |
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; FALLBACK-NEXT: bb.0.entry:
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; FALLBACK-NEXT: liveins: $w0, $w1
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;
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; FALLBACK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
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; FALLBACK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
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; FALLBACK: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]
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; FALLBACK: $w0 = COPY [[ADDWrr]]
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; FALLBACK: RET_ReallyLR implicit $w0
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%0:_(s32) = COPY $w0
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%1:_(s32) = COPY $w1
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%2:gpr(s32) = G_ADD %1, %0
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$w0 = COPY %2(s32)
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RET_ReallyLR implicit $w0
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...
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