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168 lines
7.7 KiB
168 lines
7.7 KiB
4 months ago
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s
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# IT-block with 2 statements, which we don't support yet, so check that we do
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# not remove any of the iteration count statements.
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--- |
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define hidden arm_aapcs_vfpcc void @it_block_2_stmts(float* %pSrc, float* %pDst, i32 %blockSize) local_unnamed_addr #0 {
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entry:
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%mul = shl i32 %blockSize, 1
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%0 = add i32 %mul, 3
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%1 = icmp slt i32 %mul, 4
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%smin = select i1 %1, i32 %mul, i32 4
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%2 = sub i32 %0, %smin
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%3 = lshr i32 %2, 2
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%4 = add nuw nsw i32 %3, 1
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%start = call i32 @llvm.start.loop.iterations.i32(i32 %4)
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br label %do.body
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do.body: ; preds = %do.body, %entry
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%blkCnt.0 = phi i32 [ %mul, %entry ], [ %sub, %do.body ]
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%pDst.addr.0 = phi float* [ %pDst, %entry ], [ %add.ptr4, %do.body ]
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%pSrc.addr.0 = phi float* [ %pSrc, %entry ], [ %add.ptr, %do.body ]
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%5 = phi i32 [ %start, %entry ], [ %9, %do.body ]
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%6 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %blkCnt.0)
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%input_cast = bitcast float* %pSrc.addr.0 to <4 x float>*
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%7 = tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %input_cast, i32 4, <4 x i1> %6, <4 x float> undef)
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%8 = fmul <4 x float> %7, <float 1.000000e+00, float -1.000000e+00, float 1.000000e+00, float -1.000000e+00>
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%output_cast = bitcast float* %pDst.addr.0 to <4 x float>*
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tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %8, <4 x float>* %output_cast, i32 4, <4 x i1> %6)
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%add.ptr = getelementptr inbounds float, float* %pSrc.addr.0, i32 4
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%add.ptr4 = getelementptr inbounds float, float* %pDst.addr.0, i32 4
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%sub = add nsw i32 %blkCnt.0, -4
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%9 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %5, i32 1)
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%10 = icmp ne i32 %9, 0
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br i1 %10, label %do.body, label %do.end
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do.end: ; preds = %do.body
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ret void
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}
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declare <4 x i1> @llvm.arm.mve.vctp32(i32) #1
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declare <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>*, i32 immarg, <4 x i1>, <4 x float>)
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declare void @llvm.masked.store.v4f32.p0v4f32(<4 x float>, <4 x float>*, i32 immarg, <4 x i1>)
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declare i32 @llvm.start.loop.iterations.i32(i32)
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declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
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...
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---
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name: it_block_2_stmts
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alignment: 16
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers: []
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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- { reg: '$r1', virtual-reg: '' }
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- { reg: '$r2', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 8
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offsetAdjustment: 0
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maxAlignment: 4
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack:
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- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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callSites: []
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constants:
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- id: 0
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value: '<4 x float> <float 1.000000e+00, float -1.000000e+00, float 1.000000e+00, float -1.000000e+00>'
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alignment: 16
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isTargetSpecific: false
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: it_block_2_stmts
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; CHECK: bb.0.entry:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
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; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
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; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
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; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
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; CHECK: renamable $r3, dead $cpsr = tLSLri killed renamable $r2, 1, 14 /* CC::al */, $noreg
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; CHECK: renamable $r2 = tLEApcrel %const.0, 14 /* CC::al */, $noreg
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; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg :: (load 16 from constant-pool)
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; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3
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; CHECK: bb.1.do.body (align 4):
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; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
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; CHECK: liveins: $lr, $q0, $r0, $r1
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; CHECK: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 0, $noreg
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; CHECK: renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1
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; CHECK: MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 0, killed $noreg
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; CHECK: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg
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; CHECK: renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg
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; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
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; CHECK: bb.2.do.end:
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; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
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; CHECK: bb.3 (align 16):
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; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16
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bb.0.entry:
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successors: %bb.1(0x80000000)
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liveins: $r0, $r1, $r2, $r7, $lr
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frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
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frame-setup CFI_INSTRUCTION def_cfa_offset 8
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frame-setup CFI_INSTRUCTION offset $lr, -4
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frame-setup CFI_INSTRUCTION offset $r7, -8
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renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14, $noreg
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renamable $r12 = t2MOVi 4, 14, $noreg, $noreg
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tCMPi8 renamable $r3, 4, 14, $noreg, implicit-def $cpsr
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t2IT 11, 8, implicit-def $itstate
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$r12 = t2LSLri renamable $r2, 1, 11, $cpsr, $noreg, implicit renamable $r12, implicit $itstate
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$r12 = t2LSLri renamable $r2, 1, 11, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate
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renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14, $noreg, $noreg
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renamable $r12 = t2ADDri killed renamable $r2, 3, 14, $noreg, $noreg
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renamable $r2, dead $cpsr = tMOVi8 1, 14, $noreg
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renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 19, 14, $noreg, $noreg
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renamable $r2 = tLEApcrel %const.0, 14, $noreg
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renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg :: (load 16 from constant-pool)
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$lr = t2DoLoopStart renamable $lr
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bb.1.do.body (align 4):
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successors: %bb.1(0x7c000000), %bb.2(0x04000000)
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liveins: $lr, $q0, $r0, $r1, $r3
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renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg
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MVE_VPST 2, implicit $vpr
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renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr
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renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 1, renamable $vpr, undef renamable $q1
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MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 1, killed renamable $vpr
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renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14, $noreg
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renamable $lr = t2LoopDec killed renamable $lr, 1
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renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14, $noreg
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renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 4, 14, $noreg
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t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr
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tB %bb.2, 14, $noreg
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bb.2.do.end:
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tPOP_RET 14, $noreg, def $r7, def $pc
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bb.3 (align 16):
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CONSTPOOL_ENTRY 0, %const.0, 16
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...
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