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124 lines
5.3 KiB
124 lines
5.3 KiB
4 months ago
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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;
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; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -tail-predication=enabled \
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; RUN: %s -o - --verify-machineinstrs | FileCheck %s --check-prefix=ENABLED
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;
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; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -tail-predication=enabled \
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; RUN: -arm-loloops-disable-tailpred %s -o - --verify-machineinstrs | \
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; RUN: FileCheck %s --check-prefix=DISABLED
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define dso_local void @check_option(i32* noalias nocapture %A, i32* noalias nocapture readonly %B, i32* noalias nocapture readonly %C, i32 %N) local_unnamed_addr #0 {
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; ENABLED-LABEL: check_option:
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; ENABLED: @ %bb.0: @ %entry
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; ENABLED-NEXT: push.w {r4, r5, r6, r7, r8, lr}
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; ENABLED-NEXT: cmp r3, #1
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; ENABLED-NEXT: blt .LBB0_4
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; ENABLED-NEXT: @ %bb.1: @ %vector.ph.preheader
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; ENABLED-NEXT: .LBB0_2: @ %vector.ph
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; ENABLED-NEXT: @ =>This Loop Header: Depth=1
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; ENABLED-NEXT: @ Child Loop BB0_3 Depth 2
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; ENABLED-NEXT: mov r12, r0
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; ENABLED-NEXT: mov r4, r2
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; ENABLED-NEXT: mov r5, r1
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; ENABLED-NEXT: mov r6, r3
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; ENABLED-NEXT: dlstp.32 lr, r6
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; ENABLED-NEXT: .LBB0_3: @ %vector.body
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; ENABLED-NEXT: @ Parent Loop BB0_2 Depth=1
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; ENABLED-NEXT: @ => This Inner Loop Header: Depth=2
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; ENABLED-NEXT: vldrw.u32 q0, [r5], #16
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; ENABLED-NEXT: vldrw.u32 q1, [r4], #16
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; ENABLED-NEXT: vadd.i32 q0, q1, q0
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; ENABLED-NEXT: vstrw.32 q0, [r12], #16
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; ENABLED-NEXT: letp lr, .LBB0_3
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; ENABLED-NEXT: b .LBB0_2
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; ENABLED-NEXT: .LBB0_4: @ %for.cond.cleanup
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; ENABLED-NEXT: pop.w {r4, r5, r6, r7, r8, pc}
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;
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; DISABLED-LABEL: check_option:
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; DISABLED: @ %bb.0: @ %entry
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; DISABLED-NEXT: push.w {r4, r5, r6, r7, r8, lr}
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; DISABLED-NEXT: cmp r3, #1
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; DISABLED-NEXT: blt .LBB0_4
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; DISABLED-NEXT: @ %bb.1: @ %vector.ph.preheader
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; DISABLED-NEXT: adds r7, r3, #3
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; DISABLED-NEXT: movs r6, #1
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; DISABLED-NEXT: bic r7, r7, #3
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; DISABLED-NEXT: subs r7, #4
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; DISABLED-NEXT: add.w r8, r6, r7, lsr #2
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; DISABLED-NEXT: .LBB0_2: @ %vector.ph
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; DISABLED-NEXT: @ =>This Loop Header: Depth=1
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; DISABLED-NEXT: @ Child Loop BB0_3 Depth 2
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; DISABLED-NEXT: mov r7, r8
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; DISABLED-NEXT: mov r12, r0
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; DISABLED-NEXT: mov r4, r2
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; DISABLED-NEXT: mov r5, r1
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; DISABLED-NEXT: mov r6, r3
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; DISABLED-NEXT: dls lr, r8
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; DISABLED-NEXT: .LBB0_3: @ %vector.body
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; DISABLED-NEXT: @ Parent Loop BB0_2 Depth=1
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; DISABLED-NEXT: @ => This Inner Loop Header: Depth=2
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; DISABLED-NEXT: mov lr, r7
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; DISABLED-NEXT: vctp.32 r6
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; DISABLED-NEXT: subs r7, #1
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; DISABLED-NEXT: subs r6, #4
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; DISABLED-NEXT: vpstt
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; DISABLED-NEXT: vldrwt.u32 q0, [r5], #16
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; DISABLED-NEXT: vldrwt.u32 q1, [r4], #16
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; DISABLED-NEXT: vadd.i32 q0, q1, q0
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; DISABLED-NEXT: vpst
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; DISABLED-NEXT: vstrwt.32 q0, [r12], #16
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; DISABLED-NEXT: le lr, .LBB0_3
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; DISABLED-NEXT: b .LBB0_2
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; DISABLED-NEXT: .LBB0_4: @ %for.cond.cleanup
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; DISABLED-NEXT: pop.w {r4, r5, r6, r7, r8, pc}
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entry:
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%cmp8 = icmp sgt i32 %N, 0
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%0 = add i32 %N, 3
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%1 = lshr i32 %0, 2
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%2 = shl nuw i32 %1, 2
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%3 = add i32 %2, -4
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%4 = lshr i32 %3, 2
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%5 = add nuw nsw i32 %4, 1
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br i1 %cmp8, label %vector.ph, label %for.cond.cleanup
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vector.ph: ; preds = %entry
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%trip.count.minus.1 = add i32 %N, -1
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%start = call i32 @llvm.start.loop.iterations.i32(i32 %5)
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br label %vector.body
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vector.body: ; preds = %vector.body, %vector.ph
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%lsr.iv17 = phi i32* [ %scevgep18, %vector.body ], [ %A, %vector.ph ]
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%lsr.iv14 = phi i32* [ %scevgep15, %vector.body ], [ %C, %vector.ph ]
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%lsr.iv = phi i32* [ %scevgep, %vector.body ], [ %B, %vector.ph ]
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%index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
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%6 = phi i32 [ %start, %vector.ph ], [ %8, %vector.body ]
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%lsr.iv13 = bitcast i32* %lsr.iv to <4 x i32>*
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%lsr.iv1416 = bitcast i32* %lsr.iv14 to <4 x i32>*
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%lsr.iv1719 = bitcast i32* %lsr.iv17 to <4 x i32>*
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%active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %N)
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%wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv13, i32 4, <4 x i1> %active.lane.mask, <4 x i32> undef)
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%wide.masked.load12 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv1416, i32 4, <4 x i1> %active.lane.mask, <4 x i32> undef)
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%7 = add nsw <4 x i32> %wide.masked.load12, %wide.masked.load
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call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %7, <4 x i32>* %lsr.iv1719, i32 4, <4 x i1> %active.lane.mask)
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%index.next = add i32 %index, 4
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%scevgep = getelementptr i32, i32* %lsr.iv, i32 4
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%scevgep15 = getelementptr i32, i32* %lsr.iv14, i32 4
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%scevgep18 = getelementptr i32, i32* %lsr.iv17, i32 4
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%8 = call i32 @llvm.loop.decrement.reg.i32(i32 %6, i32 1)
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%9 = icmp ne i32 %8, 0
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;br i1 %9, label %vector.body, label %for.cond.cleanup
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br i1 %9, label %vector.body, label %vector.ph
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for.cond.cleanup: ; preds = %vector.body, %entry
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ret void
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}
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declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>)
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declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>)
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declare i32 @llvm.start.loop.iterations.i32(i32)
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declare i32 @llvm.loop.decrement.reg.i32(i32, i32)
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declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)
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