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199 lines
6.3 KiB
199 lines
6.3 KiB
4 months ago
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; RUN: llc -mtriple=thumbv8.1m.main -mattr=+cdecp0 -mattr=+cdecp1 -mattr=+mve -verify-machineinstrs -o - %s | FileCheck %s
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; RUN: llc -mtriple=thumbv8m.main -mattr=+cdecp0 -mattr=+cdecp1 -mattr=+fp-armv8d16sp -verify-machineinstrs -o - %s | FileCheck %s
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declare float @llvm.arm.cde.vcx1.f32(i32 immarg, i32 immarg)
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declare float @llvm.arm.cde.vcx1a.f32(i32 immarg, float, i32 immarg)
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declare float @llvm.arm.cde.vcx2.f32(i32 immarg, float, i32 immarg)
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declare float @llvm.arm.cde.vcx2a.f32(i32 immarg, float, float, i32 immarg)
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declare float @llvm.arm.cde.vcx3.f32(i32 immarg, float, float, i32 immarg)
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declare float @llvm.arm.cde.vcx3a.f32(i32 immarg, float, float, float, i32 immarg)
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declare double @llvm.arm.cde.vcx1.f64(i32 immarg, i32 immarg)
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declare double @llvm.arm.cde.vcx1a.f64(i32 immarg, double, i32 immarg)
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declare double @llvm.arm.cde.vcx2.f64(i32 immarg, double, i32 immarg)
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declare double @llvm.arm.cde.vcx2a.f64(i32 immarg, double, double, i32 immarg)
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declare double @llvm.arm.cde.vcx3.f64(i32 immarg, double, double, i32 immarg)
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declare double @llvm.arm.cde.vcx3a.f64(i32 immarg, double, double, double, i32 immarg)
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define arm_aapcs_vfpcc i32 @test_vcx1_u32() {
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; CHECK-LABEL: test_vcx1_u32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vcx1 p0, s0, #11
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: bx lr
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entry:
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%0 = call float @llvm.arm.cde.vcx1.f32(i32 0, i32 11)
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%1 = bitcast float %0 to i32
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ret i32 %1
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}
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define arm_aapcs_vfpcc i32 @test_vcx1a_u32(i32 %acc) {
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; CHECK-LABEL: test_vcx1a_u32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov s0, r0
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; CHECK-NEXT: vcx1a p1, s0, #12
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: bx lr
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entry:
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%0 = bitcast i32 %acc to float
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%1 = call float @llvm.arm.cde.vcx1a.f32(i32 1, float %0, i32 12)
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%2 = bitcast float %1 to i32
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ret i32 %2
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}
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define arm_aapcs_vfpcc i32 @test_vcx2_u32(i32 %n) {
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; CHECK-LABEL: test_vcx2_u32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov s0, r0
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; CHECK-NEXT: vcx2 p0, s0, s0, #21
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: bx lr
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entry:
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%0 = bitcast i32 %n to float
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%1 = call float @llvm.arm.cde.vcx2.f32(i32 0, float %0, i32 21)
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%2 = bitcast float %1 to i32
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ret i32 %2
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}
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define arm_aapcs_vfpcc i32 @test_vcx2a_u32(i32 %acc, i32 %n) {
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; CHECK-LABEL: test_vcx2a_u32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov s0, r1
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; CHECK-NEXT: vmov s2, r0
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; CHECK-NEXT: vcx2a p0, s2, s0, #22
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; CHECK-NEXT: vmov r0, s2
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; CHECK-NEXT: bx lr
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entry:
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%0 = bitcast i32 %acc to float
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%1 = bitcast i32 %n to float
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%2 = call float @llvm.arm.cde.vcx2a.f32(i32 0, float %0, float %1, i32 22)
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%3 = bitcast float %2 to i32
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ret i32 %3
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}
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define arm_aapcs_vfpcc i32 @test_vcx3_u32(i32 %n, i32 %m) {
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; CHECK-LABEL: test_vcx3_u32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov s0, r1
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; CHECK-NEXT: vmov s2, r0
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; CHECK-NEXT: vcx3 p1, s0, s2, s0, #3
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: bx lr
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entry:
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%0 = bitcast i32 %n to float
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%1 = bitcast i32 %m to float
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%2 = call float @llvm.arm.cde.vcx3.f32(i32 1, float %0, float %1, i32 3)
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%3 = bitcast float %2 to i32
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ret i32 %3
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}
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define arm_aapcs_vfpcc i32 @test_vcx3a_u32(i32 %acc, i32 %n, i32 %m) {
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; CHECK-LABEL: test_vcx3a_u32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov s0, r2
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; CHECK-NEXT: vmov s2, r1
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; CHECK-NEXT: vmov s4, r0
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; CHECK-NEXT: vcx3a p0, s4, s2, s0, #5
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; CHECK-NEXT: vmov r0, s4
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; CHECK-NEXT: bx lr
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entry:
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%0 = bitcast i32 %acc to float
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%1 = bitcast i32 %n to float
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%2 = bitcast i32 %m to float
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%3 = call float @llvm.arm.cde.vcx3a.f32(i32 0, float %0, float %1, float %2, i32 5)
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%4 = bitcast float %3 to i32
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ret i32 %4
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}
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define arm_aapcs_vfpcc i64 @test_vcx1d_u64() {
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; CHECK-LABEL: test_vcx1d_u64:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vcx1 p0, d0, #11
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; CHECK-NEXT: vmov r0, r1, d0
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; CHECK-NEXT: bx lr
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entry:
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%0 = call double @llvm.arm.cde.vcx1.f64(i32 0, i32 11)
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%1 = bitcast double %0 to i64
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ret i64 %1
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}
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define arm_aapcs_vfpcc i64 @test_vcx1da_u64(i64 %acc) {
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; CHECK-LABEL: test_vcx1da_u64:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov d0, r0, r1
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; CHECK-NEXT: vcx1a p1, d0, #12
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; CHECK-NEXT: vmov r0, r1, d0
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; CHECK-NEXT: bx lr
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entry:
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%0 = bitcast i64 %acc to double
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%1 = call double @llvm.arm.cde.vcx1a.f64(i32 1, double %0, i32 12)
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%2 = bitcast double %1 to i64
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ret i64 %2
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}
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define arm_aapcs_vfpcc i64 @test_vcx2d_u64(i64 %n) {
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; CHECK-LABEL: test_vcx2d_u64:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov d0, r0, r1
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; CHECK-NEXT: vcx2 p0, d0, d0, #21
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; CHECK-NEXT: vmov r0, r1, d0
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; CHECK-NEXT: bx lr
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entry:
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%0 = bitcast i64 %n to double
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%1 = call double @llvm.arm.cde.vcx2.f64(i32 0, double %0, i32 21)
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%2 = bitcast double %1 to i64
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ret i64 %2
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}
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define arm_aapcs_vfpcc i64 @test_vcx2da_u64(i64 %acc, i64 %n) {
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; CHECK-LABEL: test_vcx2da_u64:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov d0, r2, r3
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; CHECK-NEXT: vmov d1, r0, r1
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; CHECK-NEXT: vcx2a p0, d1, d0, #22
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; CHECK-NEXT: vmov r0, r1, d1
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; CHECK-NEXT: bx lr
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entry:
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%0 = bitcast i64 %acc to double
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%1 = bitcast i64 %n to double
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%2 = call double @llvm.arm.cde.vcx2a.f64(i32 0, double %0, double %1, i32 22)
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%3 = bitcast double %2 to i64
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ret i64 %3
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}
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define arm_aapcs_vfpcc i64 @test_vcx3d_u64(i64 %n, i64 %m) {
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; CHECK-LABEL: test_vcx3d_u64:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov d0, r2, r3
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; CHECK-NEXT: vmov d1, r0, r1
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; CHECK-NEXT: vcx3 p1, d0, d1, d0, #3
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; CHECK-NEXT: vmov r0, r1, d0
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; CHECK-NEXT: bx lr
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entry:
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%0 = bitcast i64 %n to double
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%1 = bitcast i64 %m to double
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%2 = call double @llvm.arm.cde.vcx3.f64(i32 1, double %0, double %1, i32 3)
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%3 = bitcast double %2 to i64
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ret i64 %3
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}
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define arm_aapcs_vfpcc i64 @test_vcx3da_u64(i64 %acc, i64 %n, i64 %m) {
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; CHECK-LABEL: test_vcx3da_u64:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: ldrd lr, r12, [sp, #8]
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; CHECK-DAG: vmov [[D0:d.*]], r0, r1
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; CHECK-DAG: vmov [[D1:d.*]], r2, r3
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; CHECK-DAG: vmov [[D2:d.*]], lr, r12
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; CHECK-NEXT: vcx3a p0, [[D0]], [[D1]], [[D2]], #5
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; CHECK-NEXT: vmov r0, r1, [[D0]]
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; CHECK-NEXT: pop {r7, pc}
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entry:
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%0 = bitcast i64 %acc to double
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%1 = bitcast i64 %n to double
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%2 = bitcast i64 %m to double
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%3 = call double @llvm.arm.cde.vcx3a.f64(i32 0, double %0, double %1, double %2, i32 5)
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%4 = bitcast double %3 to i64
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ret i64 %4
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}
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