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76 lines
1.9 KiB
76 lines
1.9 KiB
4 months ago
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instcombine -S | FileCheck %s
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; These would crash if we didn't check for a negative shift.
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; https://llvm.org/bugs/show_bug.cgi?id=12967
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define void @pr12967() {
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; CHECK-LABEL: @pr12967(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label %loop
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; CHECK: loop:
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; CHECK-NEXT: br label %loop
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;
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entry:
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br label %loop
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loop:
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%c = phi i32 [ %shl, %loop ], [ undef, %entry ]
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%shr = shl i32 %c, 7
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%shl = lshr i32 %shr, -2
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br label %loop
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}
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; https://llvm.org/bugs/show_bug.cgi?id=26760
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define void @pr26760() {
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; CHECK-LABEL: @pr26760(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label %loop
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; CHECK: loop:
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; CHECK-NEXT: br label %loop
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;
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entry:
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br label %loop
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loop:
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%c = phi i32 [ %shl, %loop ], [ undef, %entry ]
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%shr = lshr i32 %c, 7
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%shl = shl i32 %shr, -2
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br label %loop
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}
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; Converting the 2 shifts to SHL 6 without the AND is wrong.
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; https://llvm.org/bugs/show_bug.cgi?id=8547
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define i32 @pr8547(i32* %g) {
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; CHECK-LABEL: @pr8547(
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; CHECK-NEXT: codeRepl:
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; CHECK-NEXT: br label %for.cond
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; CHECK: for.cond:
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; CHECK-NEXT: [[STOREMERGE:%.*]] = phi i32 [ 0, %codeRepl ], [ 5, %for.cond ]
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; CHECK-NEXT: store i32 [[STOREMERGE]], i32* %g, align 4
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; CHECK-NEXT: [[TMP0:%.*]] = shl nuw nsw i32 [[STOREMERGE]], 6
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; CHECK-NEXT: [[CONV2:%.*]] = and i32 [[TMP0]], 64
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; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[CONV2]], 0
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; CHECK-NEXT: br i1 [[TOBOOL]], label %for.cond, label %codeRepl2
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; CHECK: codeRepl2:
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; CHECK-NEXT: ret i32 [[CONV2]]
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;
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codeRepl:
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br label %for.cond
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for.cond:
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%storemerge = phi i32 [ 0, %codeRepl ], [ 5, %for.cond ]
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store i32 %storemerge, i32* %g, align 4
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%shl = shl i32 %storemerge, 30
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%conv2 = lshr i32 %shl, 24
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%tobool = icmp eq i32 %conv2, 0
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br i1 %tobool, label %for.cond, label %codeRepl2
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codeRepl2:
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ret i32 %conv2
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}
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