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146 lines
5.4 KiB
146 lines
5.4 KiB
4 months ago
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/*
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Copyright (c) 2020 Dario Mambro ( dario.mambro@gmail.com )
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*/
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/* Copyright (c) 2013 Julien Pommier ( pommier@modartt.com )
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Redistribution and use of the Software in source and binary forms,
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with or without modification, is permitted provided that the
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following conditions are met:
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- Neither the names of NCAR's Computational and Information Systems
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Laboratory, the University Corporation for Atmospheric Research,
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nor the names of its sponsors or contributors may be used to
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endorse or promote products derived from this Software without
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specific prior written permission.
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- Redistributions of source code must retain the above copyright
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notices, this list of conditions, and the disclaimer below.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions, and the disclaimer below in the
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documentation and/or other materials provided with the
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distribution.
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THIS SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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NONINFRINGEMENT. IN NO EVENT SHALL THE CONTRIBUTORS OR COPYRIGHT
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HOLDERS BE LIABLE FOR ANY CLAIM, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
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SOFTWARE.
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*/
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#ifndef PF_AVX_DBL_H
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#define PF_AVX_DBL_H
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/*
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vector support macros: the rest of the code is independant of
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AVX -- adding support for other platforms with 4-element
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vectors should be limited to these macros
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*/
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/*
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AVX support macros
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*/
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#if !defined(SIMD_SZ) && !defined(PFFFT_SIMD_DISABLE) && !defined(PFFFT_AVX_DISABLE) && defined(__AVX__)
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#pragma message( __FILE__ ": AVX macros are defined" )
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#include <immintrin.h>
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typedef __m256d v4sf;
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/* 4 doubles by simd vector */
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# define SIMD_SZ 4
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typedef union v4sf_union {
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v4sf v;
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double f[SIMD_SZ];
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} v4sf_union;
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# define VARCH "AVX"
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# define VREQUIRES_ALIGN 1
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# define VZERO() _mm256_setzero_pd()
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# define VMUL(a,b) _mm256_mul_pd(a,b)
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# define VADD(a,b) _mm256_add_pd(a,b)
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# define VMADD(a,b,c) _mm256_add_pd(_mm256_mul_pd(a,b), c)
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# define VSUB(a,b) _mm256_sub_pd(a,b)
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# define LD_PS1(p) _mm256_set1_pd(p)
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# define VLOAD_UNALIGNED(ptr) _mm256_loadu_pd(ptr)
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# define VLOAD_ALIGNED(ptr) _mm256_load_pd(ptr)
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/* INTERLEAVE2 (in1, in2, out1, out2) pseudo code:
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out1 = [ in1[0], in2[0], in1[1], in2[1] ]
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out2 = [ in1[2], in2[2], in1[3], in2[3] ]
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*/
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# define INTERLEAVE2(in1, in2, out1, out2) { \
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__m128d low1__ = _mm256_castpd256_pd128(in1); \
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__m128d low2__ = _mm256_castpd256_pd128(in2); \
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__m128d high1__ = _mm256_extractf128_pd(in1, 1); \
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__m128d high2__ = _mm256_extractf128_pd(in2, 1); \
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__m256d tmp__ = _mm256_insertf128_pd( \
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_mm256_castpd128_pd256(_mm_shuffle_pd(low1__, low2__, 0)), \
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_mm_shuffle_pd(low1__, low2__, 3), \
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1); \
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out2 = _mm256_insertf128_pd( \
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_mm256_castpd128_pd256(_mm_shuffle_pd(high1__, high2__, 0)), \
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_mm_shuffle_pd(high1__, high2__, 3), \
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1); \
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out1 = tmp__; \
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}
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/*UNINTERLEAVE2(in1, in2, out1, out2) pseudo code:
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out1 = [ in1[0], in1[2], in2[0], in2[2] ]
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out2 = [ in1[1], in1[3], in2[1], in2[3] ]
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*/
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# define UNINTERLEAVE2(in1, in2, out1, out2) { \
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__m128d low1__ = _mm256_castpd256_pd128(in1); \
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__m128d low2__ = _mm256_castpd256_pd128(in2); \
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__m128d high1__ = _mm256_extractf128_pd(in1, 1); \
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__m128d high2__ = _mm256_extractf128_pd(in2, 1); \
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__m256d tmp__ = _mm256_insertf128_pd( \
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_mm256_castpd128_pd256(_mm_shuffle_pd(low1__, high1__, 0)), \
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_mm_shuffle_pd(low2__, high2__, 0), \
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1); \
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out2 = _mm256_insertf128_pd( \
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_mm256_castpd128_pd256(_mm_shuffle_pd(low1__, high1__, 3)), \
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_mm_shuffle_pd(low2__, high2__, 3), \
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1); \
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out1 = tmp__; \
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}
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# define VTRANSPOSE4(row0, row1, row2, row3) { \
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__m256d tmp3, tmp2, tmp1, tmp0; \
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\
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tmp0 = _mm256_shuffle_pd((row0),(row1), 0x0); \
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tmp2 = _mm256_shuffle_pd((row0),(row1), 0xF); \
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tmp1 = _mm256_shuffle_pd((row2),(row3), 0x0); \
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tmp3 = _mm256_shuffle_pd((row2),(row3), 0xF); \
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\
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(row0) = _mm256_permute2f128_pd(tmp0, tmp1, 0x20); \
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(row1) = _mm256_permute2f128_pd(tmp2, tmp3, 0x20); \
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(row2) = _mm256_permute2f128_pd(tmp0, tmp1, 0x31); \
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(row3) = _mm256_permute2f128_pd(tmp2, tmp3, 0x31); \
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}
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/*VSWAPHL(a, b) pseudo code:
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return [ b[0], b[1], a[2], a[3] ]
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*/
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# define VSWAPHL(a,b) \
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_mm256_insertf128_pd(_mm256_castpd128_pd256(_mm256_castpd256_pd128(b)), _mm256_extractf128_pd(a, 1), 1)
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/* reverse/flip all floats */
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# define VREV_S(a) _mm256_insertf128_pd(_mm256_castpd128_pd256(_mm_permute_pd(_mm256_extractf128_pd(a, 1),1)), _mm_permute_pd(_mm256_castpd256_pd128(a), 1), 1)
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/* reverse/flip complex floats */
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# define VREV_C(a) _mm256_insertf128_pd(_mm256_castpd128_pd256(_mm256_extractf128_pd(a, 1)), _mm256_castpd256_pd128(a), 1)
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# define VALIGNED(ptr) ((((uintptr_t)(ptr)) & 0x1F) == 0)
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#endif
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#endif /* PF_AVX_DBL_H */
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