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88 lines
3.5 KiB
88 lines
3.5 KiB
4 months ago
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/* Copyright (c) 2013 Julien Pommier ( pommier@modartt.com )
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Redistribution and use of the Software in source and binary forms,
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with or without modification, is permitted provided that the
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following conditions are met:
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- Neither the names of NCAR's Computational and Information Systems
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Laboratory, the University Corporation for Atmospheric Research,
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nor the names of its sponsors or contributors may be used to
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endorse or promote products derived from this Software without
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specific prior written permission.
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- Redistributions of source code must retain the above copyright
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notices, this list of conditions, and the disclaimer below.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions, and the disclaimer below in the
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documentation and/or other materials provided with the
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distribution.
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THIS SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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NONINFRINGEMENT. IN NO EVENT SHALL THE CONTRIBUTORS OR COPYRIGHT
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HOLDERS BE LIABLE FOR ANY CLAIM, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
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SOFTWARE.
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*/
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#ifndef PF_NEON_FLT_H
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#define PF_NEON_FLT_H
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/*
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ARM NEON support macros
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*/
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#if !defined(PFFFT_SIMD_DISABLE) && defined(PFFFT_ENABLE_NEON) && (defined(__arm__) || defined(__aarch64__) || defined(__arm64__))
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#pragma message( __FILE__ ": ARM NEON macros are defined" )
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# include <arm_neon.h>
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typedef float32x4_t v4sf;
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# define SIMD_SZ 4
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typedef union v4sf_union {
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v4sf v;
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float f[SIMD_SZ];
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} v4sf_union;
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# define VARCH "NEON"
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# define VREQUIRES_ALIGN 0 /* usually no alignment required */
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# define VZERO() vdupq_n_f32(0)
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# define VMUL(a,b) vmulq_f32(a,b)
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# define VADD(a,b) vaddq_f32(a,b)
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# define VMADD(a,b,c) vmlaq_f32(c,a,b)
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# define VSUB(a,b) vsubq_f32(a,b)
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# define LD_PS1(p) vld1q_dup_f32(&(p))
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# define VLOAD_UNALIGNED(ptr) (*((v4sf*)(ptr)))
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# define VLOAD_ALIGNED(ptr) (*((v4sf*)(ptr)))
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# define INTERLEAVE2(in1, in2, out1, out2) { float32x4x2_t tmp__ = vzipq_f32(in1,in2); out1=tmp__.val[0]; out2=tmp__.val[1]; }
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# define UNINTERLEAVE2(in1, in2, out1, out2) { float32x4x2_t tmp__ = vuzpq_f32(in1,in2); out1=tmp__.val[0]; out2=tmp__.val[1]; }
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# define VTRANSPOSE4(x0,x1,x2,x3) { \
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float32x4x2_t t0_ = vzipq_f32(x0, x2); \
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float32x4x2_t t1_ = vzipq_f32(x1, x3); \
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float32x4x2_t u0_ = vzipq_f32(t0_.val[0], t1_.val[0]); \
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float32x4x2_t u1_ = vzipq_f32(t0_.val[1], t1_.val[1]); \
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x0 = u0_.val[0]; x1 = u0_.val[1]; x2 = u1_.val[0]; x3 = u1_.val[1]; \
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}
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// marginally faster version
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//# define VTRANSPOSE4(x0,x1,x2,x3) { asm("vtrn.32 %q0, %q1;\n vtrn.32 %q2,%q3\n vswp %f0,%e2\n vswp %f1,%e3" : "+w"(x0), "+w"(x1), "+w"(x2), "+w"(x3)::); }
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# define VSWAPHL(a,b) vcombine_f32(vget_low_f32(b), vget_high_f32(a))
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/* reverse/flip all floats */
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# define VREV_S(a) vcombine_f32(vrev64_f32(vget_high_f32(a)), vrev64_f32(vget_low_f32(a)))
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/* reverse/flip complex floats */
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# define VREV_C(a) vextq_f32(a, a, 2)
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# define VALIGNED(ptr) ((((uintptr_t)(ptr)) & 0x3) == 0)
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#else
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/* #pragma message( __FILE__ ": ARM NEON macros are not defined" ) */
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#endif
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#endif /* PF_NEON_FLT_H */
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