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19 lines
972 B
19 lines
972 B
4 months ago
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; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=VI -check-prefix=GCN %s
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; Make sure there isn't an extra space between the instruction name and first operands.
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; GCN-LABEL: {{^}}add_f32:
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; SI-DAG: s_load_dword [[SREGA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
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; SI-DAG: s_load_dword [[SREGB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
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; VI-DAG: s_load_dword [[SREGA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
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; VI-DAG: s_load_dword [[SREGB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
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; GCN: v_mov_b32_e32 [[VREGB:v[0-9]+]], [[SREGB]]
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; GCN: v_add_f32_e32 [[RESULT:v[0-9]+]], [[SREGA]], [[VREGB]]
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; GCN: buffer_store_dword [[RESULT]],
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define void @add_f32(float addrspace(1)* %out, float %a, float %b) {
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%result = fadd float %a, %b
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store float %result, float addrspace(1)* %out
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ret void
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}
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