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59 lines
919 B
59 lines
919 B
4 months ago
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# RUN: llvm-mc -disassemble -triple armv8 -mattr=+db -show-encoding < %s | FileCheck %s
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# New v8 ARM instructions
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# HLT
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0x70 0x00 0x00 0xe1
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# CHECK: hlt #0
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0x7f 0xff 0x0f 0xe1
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# CHECK: hlt #65535
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0x59 0xf0 0x7f 0xf5
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0x51 0xf0 0x7f 0xf5
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0x55 0xf0 0x7f 0xf5
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0x5d 0xf0 0x7f 0xf5
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# CHECK: dmb ishld
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# CHECK: dmb oshld
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# CHECK: dmb nshld
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# CHECK: dmb ld
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0x05 0xf0 0x20 0xe3
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# CHECK: sevl
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# These are the only coprocessor instructions that remain defined in ARMv8
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# (The operations on p10/p11 disassemble into FP/NEON instructions)
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0x10 0x0e 0x00 0xee
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# CHECK: mcr p14
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0x10 0x0f 0x00 0xee
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# CHECK: mcr p15
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0x10 0x0e 0x10 0xee
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# CHECK: mrc p14
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0x10 0x0f 0x10 0xee
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# CHECK: mrc p15
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0x00 0x0e 0x40 0xec
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# CHECK: mcrr p14
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0x00 0x0f 0x40 0xec
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# CHECK: mcrr p15
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0x00 0x0e 0x50 0xec
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# CHECK: mrrc p14
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0x00 0x0f 0x50 0xec
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# CHECK: mrrc p15
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0x00 0x0e 0x80 0xec
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# CHECK: stc p14
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0x00 0x0e 0x90 0xec
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# CHECK: ldc p14
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