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62 lines
2.1 KiB
62 lines
2.1 KiB
4 months ago
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef HI3660_HKADC_H
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#define HI3660_HKADC_H
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#define HKADC_SSI_REG_BASE 0xE82B8000
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#define HKADC_DSP_START_REG (HKADC_SSI_REG_BASE + 0x000)
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#define HKADC_WR_NUM_REG (HKADC_SSI_REG_BASE + 0x008)
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#define HKADC_DSP_START_CLR_REG (HKADC_SSI_REG_BASE + 0x01C)
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#define HKADC_WR01_DATA_REG (HKADC_SSI_REG_BASE + 0x020)
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#define WR1_WRITE_MODE (1U << 31)
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#define WR1_READ_MODE (0 << 31)
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#define WR1_ADDR(x) (((x) & 0x7F) << 24)
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#define WR1_DATA(x) (((x) & 0xFF) << 16)
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#define WR0_WRITE_MODE (1 << 15)
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#define WR0_READ_MODE (0 << 15)
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#define WR0_ADDR(x) (((x) & 0x7F) << 8)
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#define WR0_DATA(x) ((x) & 0xFF)
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#define HKADC_WR23_DATA_REG (HKADC_SSI_REG_BASE + 0x024)
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#define HKADC_WR45_DATA_REG (HKADC_SSI_REG_BASE + 0x028)
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#define HKADC_DELAY01_REG (HKADC_SSI_REG_BASE + 0x030)
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#define HKADC_DELAY23_REG (HKADC_SSI_REG_BASE + 0x034)
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#define HKADC_DELAY45_REG (HKADC_SSI_REG_BASE + 0x038)
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#define HKADC_DSP_RD2_DATA_REG (HKADC_SSI_REG_BASE + 0x048)
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#define HKADC_DSP_RD3_DATA_REG (HKADC_SSI_REG_BASE + 0x04C)
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/* HKADC Internal Registers */
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#define HKADC_CTRL_ADDR 0x00
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#define HKADC_START_ADDR 0x01
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#define HKADC_DATA1_ADDR 0x03 /* high 8 bits */
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#define HKADC_DATA0_ADDR 0x04 /* low 8 bits */
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#define HKADC_MODE_CFG 0x0A
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#define HKADC_VALUE_HIGH 0x0FF0
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#define HKADC_VALUE_LOW 0x000F
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#define HKADC_VALID_VALUE 0x0FFF
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#define HKADC_CHANNEL_MAX 15
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#define HKADC_VREF_1V8 1800
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#define HKADC_ACCURACY 0x0FFF
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#define HKADC_WR01_VALUE ((HKADC_START_ADDR << 24) | \
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(0x1 << 16))
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#define HKADC_WR23_VALUE ((0x1u << 31) | \
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(HKADC_DATA0_ADDR << 24) | \
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(1 << 15) | \
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(HKADC_DATA1_ADDR << 8))
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#define HKADC_WR45_VALUE (0x80)
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#define HKADC_CHANNEL0_DELAY01_VALUE ((0x0700 << 16) | 0xFFFF)
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#define HKADC_DELAY01_VALUE ((0x0700 << 16) | 0x0200)
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#define HKADC_DELAY23_VALUE ((0x00C8 << 16) | 0x00C8)
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#define START_DELAY_TIMEOUT 2000
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#define HKADC_WR_NUM_VALUE 4
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#endif /* HI3660_HKADC_H */
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