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93 lines
2.3 KiB
93 lines
2.3 KiB
7 months ago
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/*
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* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SMMU_H
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#define SMMU_H
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#include <lib/mmio.h>
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#include <memctrl_v2.h>
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#include <tegra_def.h>
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#define SMMU_CBn_ACTLR (0x4U)
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/*******************************************************************************
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* SMMU Global Secure Aux. Configuration Register
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******************************************************************************/
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#define SMMU_GSR0_SECURE_ACR 0x10U
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#define SMMU_GNSR_ACR (SMMU_GSR0_SECURE_ACR + 0x400U)
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#define SMMU_GSR0_PGSIZE_SHIFT 16U
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#define SMMU_GSR0_PGSIZE_4K (0U << SMMU_GSR0_PGSIZE_SHIFT)
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#define SMMU_GSR0_PGSIZE_64K (1U << SMMU_GSR0_PGSIZE_SHIFT)
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#define SMMU_ACR_CACHE_LOCK_ENABLE_BIT (1ULL << 26U)
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#define SMMU_GSR0_PER (0x20200U)
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/*******************************************************************************
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* SMMU Global Aux. Control Register
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******************************************************************************/
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#define SMMU_CBn_ACTLR_CPRE_BIT (1ULL << 1U)
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/* SMMU IDs currently supported by the driver */
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enum {
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TEGRA_SMMU0 = 0U,
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TEGRA_SMMU1 = 1U,
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TEGRA_SMMU2 = 2U
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};
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static inline uint32_t tegra_smmu_read_32(uint32_t smmu_id, uint32_t off)
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{
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uint32_t ret = 0U;
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#if defined(TEGRA_SMMU0_BASE)
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if (smmu_id == TEGRA_SMMU0) {
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ret = mmio_read_32(TEGRA_SMMU0_BASE + (uint64_t)off);
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}
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#endif
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#if defined(TEGRA_SMMU1_BASE)
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if (smmu_id == TEGRA_SMMU1) {
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ret = mmio_read_32(TEGRA_SMMU1_BASE + (uint64_t)off);
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}
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#endif
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#if defined(TEGRA_SMMU2_BASE)
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if (smmu_id == TEGRA_SMMU2) {
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ret = mmio_read_32(TEGRA_SMMU2_BASE + (uint64_t)off);
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}
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#endif
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return ret;
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}
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static inline void tegra_smmu_write_32(uint32_t smmu_id,
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uint32_t off, uint32_t val)
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{
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#if defined(TEGRA_SMMU0_BASE)
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if (smmu_id == TEGRA_SMMU0) {
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mmio_write_32(TEGRA_SMMU0_BASE + (uint64_t)off, val);
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}
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#endif
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#if defined(TEGRA_SMMU1_BASE)
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if (smmu_id == TEGRA_SMMU1) {
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mmio_write_32(TEGRA_SMMU1_BASE + (uint64_t)off, val);
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}
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#endif
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#if defined(TEGRA_SMMU2_BASE)
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if (smmu_id == TEGRA_SMMU2) {
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mmio_write_32(TEGRA_SMMU2_BASE + (uint64_t)off, val);
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}
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#endif
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}
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void tegra_smmu_init(void);
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void tegra_smmu_verify(void);
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uint32_t plat_get_num_smmu_devices(void);
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#endif /* SMMU_H */
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