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218 lines
6.9 KiB
218 lines
6.9 KiB
4 months ago
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/****************************************************************************
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****************************************************************************
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***
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*** This header was automatically generated from a Linux kernel header
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*** of the same name, to make information necessary for userspace to
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*** call into the kernel available to libc. It contains only constants,
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*** structures, and macros generated from the original header, and thus,
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*** contains no copyrightable information.
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***
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*** To edit the content of this header, modify the corresponding
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*** source file (e.g. under external/kernel-headers/original/) then
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*** run bionic/libc/kernel/tools/update_all.py
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***
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*** Any manual change here will be lost the next time this script will
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*** be run. You've been warned!
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***
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****************************************************************************
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****************************************************************************/
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#ifndef __MSM_DRM_H__
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#define __MSM_DRM_H__
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#include "drm.h"
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#include "sde_drm.h"
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#ifdef __cplusplus
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#endif
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#define MSM_PIPE_NONE 0x00
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#define MSM_PIPE_2D0 0x01
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#define MSM_PIPE_2D1 0x02
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#define MSM_PIPE_3D0 0x10
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#define MSM_PIPE_ID_MASK 0xffff
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#define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK)
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#define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK)
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struct drm_msm_timespec {
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__s64 tv_sec;
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__s64 tv_nsec;
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};
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#define HDR_PRIMARIES_COUNT 3
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#define HDR_EOTF_SDR_LUM_RANGE 0x0
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#define HDR_EOTF_HDR_LUM_RANGE 0x1
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#define HDR_EOTF_SMTPE_ST2084 0x2
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#define HDR_EOTF_HLG 0x3
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#define DRM_MSM_EXT_HDR_METADATA
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struct drm_msm_ext_hdr_metadata {
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__u32 hdr_state;
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__u32 eotf;
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__u32 hdr_supported;
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__u32 display_primaries_x[HDR_PRIMARIES_COUNT];
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__u32 display_primaries_y[HDR_PRIMARIES_COUNT];
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__u32 white_point_x;
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__u32 white_point_y;
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__u32 max_luminance;
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__u32 min_luminance;
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__u32 max_content_light_level;
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__u32 max_average_light_level;
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};
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#define DRM_MSM_EXT_HDR_PROPERTIES
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struct drm_msm_ext_hdr_properties {
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__u8 hdr_metadata_type_one;
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__u32 hdr_supported;
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__u32 hdr_eotf;
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__u32 hdr_max_luminance;
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__u32 hdr_avg_luminance;
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__u32 hdr_min_luminance;
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};
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#define MSM_PARAM_GPU_ID 0x01
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#define MSM_PARAM_GMEM_SIZE 0x02
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#define MSM_PARAM_CHIP_ID 0x03
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#define MSM_PARAM_MAX_FREQ 0x04
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#define MSM_PARAM_TIMESTAMP 0x05
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struct drm_msm_param {
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__u32 pipe;
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__u32 param;
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__u64 value;
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};
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#define MSM_BO_SCANOUT 0x00000001
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#define MSM_BO_GPU_READONLY 0x00000002
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#define MSM_BO_CACHE_MASK 0x000f0000
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#define MSM_BO_CACHED 0x00010000
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#define MSM_BO_WC 0x00020000
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#define MSM_BO_UNCACHED 0x00040000
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#define MSM_BO_FLAGS (MSM_BO_SCANOUT | MSM_BO_GPU_READONLY | MSM_BO_CACHED | MSM_BO_WC | MSM_BO_UNCACHED)
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struct drm_msm_gem_new {
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__u64 size;
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__u32 flags;
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__u32 handle;
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};
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struct drm_msm_gem_info {
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__u32 handle;
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__u32 pad;
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__u64 offset;
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};
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#define MSM_PREP_READ 0x01
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#define MSM_PREP_WRITE 0x02
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#define MSM_PREP_NOSYNC 0x04
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#define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC)
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struct drm_msm_gem_cpu_prep {
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__u32 handle;
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__u32 op;
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struct drm_msm_timespec timeout;
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};
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struct drm_msm_gem_cpu_fini {
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__u32 handle;
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};
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struct drm_msm_gem_submit_reloc {
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__u32 submit_offset;
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__u32 or;
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__s32 shift;
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__u32 reloc_idx;
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__u64 reloc_offset;
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};
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#define MSM_SUBMIT_CMD_BUF 0x0001
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#define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002
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#define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003
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struct drm_msm_gem_submit_cmd {
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__u32 type;
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__u32 submit_idx;
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__u32 submit_offset;
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__u32 size;
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__u32 pad;
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__u32 nr_relocs;
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__u64 relocs;
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};
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#define MSM_SUBMIT_BO_READ 0x0001
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#define MSM_SUBMIT_BO_WRITE 0x0002
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#define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE)
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struct drm_msm_gem_submit_bo {
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__u32 flags;
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__u32 handle;
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__u64 presumed;
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};
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#define MSM_SUBMIT_NO_IMPLICIT 0x80000000
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#define MSM_SUBMIT_FENCE_FD_IN 0x40000000
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#define MSM_SUBMIT_FENCE_FD_OUT 0x20000000
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#define MSM_SUBMIT_FLAGS (MSM_SUBMIT_NO_IMPLICIT | MSM_SUBMIT_FENCE_FD_IN | MSM_SUBMIT_FENCE_FD_OUT | 0)
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struct drm_msm_gem_submit {
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__u32 flags;
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__u32 fence;
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__u32 nr_bos;
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__u32 nr_cmds;
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__u64 bos;
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__u64 cmds;
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__s32 fence_fd;
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};
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struct drm_msm_wait_fence {
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__u32 fence;
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__u32 pad;
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struct drm_msm_timespec timeout;
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};
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#define MSM_MADV_WILLNEED 0
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#define MSM_MADV_DONTNEED 1
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#define __MSM_MADV_PURGED 2
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struct drm_msm_gem_madvise {
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__u32 handle;
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__u32 madv;
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__u32 retained;
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};
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#define DISPLAY_PRIMARIES_WX 0
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#define DISPLAY_PRIMARIES_WY 1
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#define DISPLAY_PRIMARIES_RX 2
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#define DISPLAY_PRIMARIES_RY 3
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#define DISPLAY_PRIMARIES_GX 4
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#define DISPLAY_PRIMARIES_GY 5
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#define DISPLAY_PRIMARIES_BX 6
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#define DISPLAY_PRIMARIES_BY 7
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#define DISPLAY_PRIMARIES_MAX 8
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struct drm_panel_hdr_properties {
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__u32 hdr_enabled;
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__u32 display_primaries[DISPLAY_PRIMARIES_MAX];
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__u32 peak_brightness;
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__u32 blackness_level;
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};
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struct drm_msm_event_req {
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__u32 object_id;
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__u32 object_type;
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__u32 event;
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__u64 client_context;
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__u32 index;
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};
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struct drm_msm_event_resp {
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struct drm_event base;
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struct drm_msm_event_req info;
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__u8 data[];
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};
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#define DRM_MSM_GET_PARAM 0x00
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#define DRM_MSM_GEM_NEW 0x02
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#define DRM_MSM_GEM_INFO 0x03
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#define DRM_MSM_GEM_CPU_PREP 0x04
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#define DRM_MSM_GEM_CPU_FINI 0x05
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#define DRM_MSM_GEM_SUBMIT 0x06
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#define DRM_MSM_WAIT_FENCE 0x07
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#define DRM_MSM_GEM_MADVISE 0x08
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#define DRM_SDE_WB_CONFIG 0x40
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#define DRM_MSM_REGISTER_EVENT 0x41
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#define DRM_MSM_DEREGISTER_EVENT 0x42
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#define DRM_MSM_RMFB2 0x43
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#define DRM_EVENT_HISTOGRAM 0x80000000
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#define DRM_EVENT_AD_BACKLIGHT 0x80000001
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#define DRM_EVENT_CRTC_POWER 0x80000002
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#define DRM_EVENT_SYS_BACKLIGHT 0x80000003
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#define DRM_EVENT_SDE_POWER 0x80000004
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#define DRM_EVENT_IDLE_NOTIFY 0x80000005
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#define DRM_EVENT_PANEL_DEAD 0x80000006
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#define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
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#define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
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#define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)
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#define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)
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#define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
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#define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
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#define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
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#define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise)
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#define DRM_IOCTL_SDE_WB_CONFIG DRM_IOW((DRM_COMMAND_BASE + DRM_SDE_WB_CONFIG), struct sde_drm_wb_cfg)
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#define DRM_IOCTL_MSM_REGISTER_EVENT DRM_IOW((DRM_COMMAND_BASE + DRM_MSM_REGISTER_EVENT), struct drm_msm_event_req)
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#define DRM_IOCTL_MSM_DEREGISTER_EVENT DRM_IOW((DRM_COMMAND_BASE + DRM_MSM_DEREGISTER_EVENT), struct drm_msm_event_req)
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#define DRM_IOCTL_MSM_RMFB2 DRM_IOW((DRM_COMMAND_BASE + DRM_MSM_RMFB2), unsigned int)
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#ifdef __cplusplus
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#endif
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#endif
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