v811_spc009/external/vixl/test/aarch32/config/cond-rd-rn-t32.json

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// Test description for instructions of the following form:
//   MNEMONIC{<c>}.N <Rd>, <Rm>
//   MNEMONIC{<c>}.W <Rd>, <Rm>

{
  "mnemonics" : [
    "Clz",   // CLZ{<c>}{<q>} <Rd>, <Rm> ; T1
    "Rbit",  // RBIT{<c>}{<q>} <Rd>, <Rm> ; T1
    "Rev",   // REV{<c>}{<q>} <Rd>, <Rm> ; T1
             // REV{<c>}{<q>} <Rd>, <Rm> ; T2
    "Rev16", // REV16{<c>}{<q>} <Rd>, <Rm> ; T1
             // REV16{<c>}{<q>} <Rd>, <Rm> ; T2
    "Revsh", // REVSH{<c>}{<q>} <Rd>, <Rm> ; T1
             // REVSH{<c>}{<q>} <Rd>, <Rm> ; T2
    "Rrx",   // RRX{<c>}{<q>} {<Rd>}, <Rm> ; T3
    "Rrxs"   // RRXS{<c>}{<q>} {<Rd>}, <Rm> ; T3
  ],
  "description" : {
    "operands": [
      {
        "name": "cond",
        "type": "Condition"
      },
      {
        "name": "rd",
        "type": "AllRegistersButPC"
      },
      {
        "name": "rn",
        "type": "AllRegistersButPC"
      }
    ],
    "inputs": [
      {
        "name": "apsr",
        "type": "NZCV"
      },
      {
        "name": "rd",
        "type": "Register"
      },
      {
        "name": "rn",
        "type": "Register"
      }
    ]
  },
  "test-files": [
    {
      "type": "assembler",
      "test-cases": [
        {
          "name": "Unconditional",
          "operands": [
            "cond", "rd", "rn"
          ],
          "operand-filter": "cond == 'al'"
        }
      ]
    },
    {
      "type": "macro-assembler",
      "test-cases": [
        {
          "name": "Operands",
          "operands": [
            "cond", "rd", "rn"
          ],
          "operand-limit": 500
        }
      ]
    },
    {
      "type": "simulator",
      "test-cases": [
        {
          "name": "Condition",
          "operands": [
            "cond"
          ],
          "inputs": [
            "apsr"
          ]
        },
        // Test combinations of registers values with rd == rn.
        {
          "name": "RdIsRn",
          "operands": [
            "rd", "rn"
          ],
          "inputs": [
            "rd", "rn"
          ],
          "operand-filter": "rd == rn",
          "input-filter": "rd == rn"
        },
        // Test combinations of registers values with rd != rn.
        {
          "name": "RdIsNotRn",
          "operands": [
            "rd", "rn"
          ],
          "inputs": [
            "rd", "rn"
          ],
          "operand-filter": "rd != rn",
          "operand-limit": 10,
          "input-filter": "rd != rn"
        }
      ]
    }
  ]
}