#ifndef __HLETH_FEPHY_FIX_H
#define __HLETH_FEPHY_FIX_H

#define CONFIG_CHIP_RESERVED17

/* fephy CRG */
#ifdef CONFIG_CHIP_RESERVED17
#define CRG_BASE				0xF8003000
#define HLETHPHY_SYSREG_REG			0x0510
#elif defined(CONFIG_CHIP_RESERVED5)
#define CRG_BASE				0xF8A22000
#define HLETHPHY_SYSREG_REG			0x0098
#endif
#define HLETH_SOFT_RESET_BIT			16
#define HLETH_CLK_ENABLE			0x1
#define HLETH_PHY_ADDR_BIT			23
#define MASK_PHY_ADDR				0x1F
/* fephy ctrl reg ,set phy addr */
#define HLETH_FEPHY_ADDR			0x0028
#define HLETH_FEPHY_SELECT			0x8
#define HLETH_FEPHY_LDO_CTRL			0x844

/* DEFAULT external phy reset pin */
#ifdef CONFIG_CHIP_RESERVED17
#define HLETH_FEPHY_RST_BASE			0x0510
#define HLETH_FEPHY_RST_BIT			16
#elif defined(CONFIG_CHIP_RESERVED5)
#define HLETH_FEPHY_RST_BASE			0x0f80
#define HLETH_FEPHY_RST_BIT			1
#endif
#define MII_EXPMD			0x1D
#define MII_EXPMA			0x1E

/* the following two copied from phy_quirk()
 * in "./drivers/net/ethernet/hleth-sf/net.c"
 */
#define PHY_ID_KSZ8051MNL		0x00221550
#define PHY_ID_KSZ8081RNB		0x00221560
#define DEFAULT_PHY_MASK		0xfffffff0

#endif