#Sample:
#/* If a bit is ignored, it can be represented by FFFF.(Example: serialNum can be represented by FF.) */
#[mfcNmae_productCode_serialNum_year_week_baseChecksum]
#    sink_ready_under340m = 1;            /* when TMDS clock under 340MHz,delay to wait sink hdcp ready */
#    sink_ready_over340m = 1;          /* when TMDS clock over 340MHz,delay to wait sink hdcp ready */
#    send_nullpacket_when_hdcp2x = 1;       /* whether send nullpacket when start hdcp2x */
#    send_avmute_pkg = 1;              /* whether send avmute package before stop hdmi output */
#    time_before_stop = 1;           /* avmute time duration before stop hdmi output */
#    time_after_start = 1;           /* avmute time duration after start hdmi output */
#    reset_delay_time = 1;           /* the time wait for the sink to reset between hdmitx stop and start */
#    fcg_delay_time = 0;            /* Pre-training Delay */
#    support_yuv444 = 1;           /*It should be supported, but not supported in sink edid. */
#    support_yuv422 = 1;
#    support_deepcolor_10 = 1;
#    support_deepcolor_12 = 1;
#    support_yuv444_deepcolor = 1;
#    support_yuv420 = 1;
#    support_yuv420_10 = 1;
#    support_yuv420_12 = 1;
#    dsc_1p2 = 1;             /* DSC_1p2 */
#    y420 = 1;             /* DSC_Native_420 */
#    all_bpp = 1;            /* DSC_ALL_bpp */
#    dsc_16bpc = 1;         /* DSC_16bpc */
#    dsc_12bpc = 1;            /* DSC_12bpc */
#    dsc_10bpc = 1;              /* DSC_10bpc */
#    dsc_max_rate = 1;        /* DSC_Max_FRL_Rate */
#    max_slice = 5;          /* DSC_MaxSlices */
#    total_chunk_bytes = 11;          /* DSC_TotalChunkBytes */
#    max_frl_rate = 3;       /* It should be supported, but not supported in sink edid. */
#    repeat_count = 1;
#    support_vic1 = 1;      /* vic1 should be supported, but not supported in sink edid. */
#    support_vic2 = 1;
#    support_vic3 = 1;
#    support_vic4 = 1;
#    support_vic5 = 1;
#    support_vic6 = 1;
#    support_vic7 = 1;
#    support_vic8 = 1;
#    support_vic9 = 1;
#    support_vic10 = 1;
#    high_reshold = 1;       /* filter out all that time of high-level less than osc_div_cnt*high_reshold*(1/24M) */
#    low_reshold = 1;        /* filter out all that time of low-level less than osc_div_cnt*low_reshold*(1/24M) */
#    force_clear_scdc = 1;       /* force to clear scdc */
#    hdr_debug_mode = 1;       /* enter or quit hdr debug mode */

#LED32H1600Y
[HSI_1_1_2014_47_86]
    time_before_stop = 1000;
    time_after_start = 800;

#24E60HR
[SKW_60_1_2008_1_76]
    time_before_stop = 120;
    reset_delay_time = 1500;

#LED24HS95
[KOA_60_1_2008_1_e6]
    time_before_stop = 120;

#LED70MU7000U
[HEC_60_1_2015_12_7e]
    time_before_stop = 120;
    reset_delay_time = 1000;

#L65M5-AD
[XMD_112_1_2018_6_8f]
    sink_ready_over340m = 200;

#42E780U
[SKW_1_1_2013_38_6f]
    time_before_stop = 120;

#MTV55K1J
[WTV_52421_1_2015_16_40]
    send_nullpacket_when_hdcp2x = 1;

#Z9G
[SNY_12005_10421_2019_1_28]
    support_yuv420 = 1;
    support_yuv420_10 = 1;
    support_yuv420_12 = 1;
    support_vic1 = 8391;
    support_vic2 = 8390;
    support_vic3 = 8388;
    max_frl_rate = 3;
    dsc_1p2 = 1;
    y420 = 1;
    dsc_12bpc = 1;
    dsc_10bpc = 1;
    dsc_max_rate = 3;
    max_slice = 5;
    total_chunk_bytes = 11;

#8K
[SHP_4491_FFFFFFFF_FF_FF_FFFF]
    repeat_count = 1;

#8K
[SHP_4485_FFFFFFFF_FF_FF_FFFF]
    repeat_count = 1;

#8K
[SHP_4488_FFFFFFFF_FF_FF_FFFF]
    repeat_count = 1;

#8K
[SHP_4494_FFFFFFFF_FF_FF_FFFF]
    repeat_count = 1;

#8K
[SHP_4506_FFFFFFFF_FF_FF_FFFF]
    repeat_count = 1;

#8K
[SHP_4507_FFFFFFFF_FF_FF_FFFF]
    repeat_count = 1;

#8K
[SHP_9301_FFFFFFFF_FF_FF_FFFF]
    repeat_count = 1;

#8K
[SHP_9304_FFFFFFFF_FF_FF_FFFF]
    repeat_count = 1;

#60SJ8500-CA
[GSM_1_16843009_2017_1_63]
    sink_ready_under340m = 800;
    time_before_stop = 100;

[SCX_FFFF_0_2018_0_FFFF]
    repeat_count = 1;

#6H70-55M2
[SKY_16_16843009_2020_8_24]
    send_avmute_pkg = 0;

#L50M5-AD
[XMD_74_1_2018_6_e6]
    sink_ready_under340m = 100;
    time_before_stop = 50;

#PLAT-760
[HWV_48_0_2019_255_79]
    send_avmute_pkg = 0;
    time_before_stop = 200;

[PHL_0_16843009_2019_16_81]
    support_yuv420 = 1;
    support_yuv420_10 = 1;
    support_yuv420_12 = 1;
    support_vic1 = 8391;
    support_vic2 = 8390;
    support_vic3 = 8388;
    max_frl_rate = 3;
    dsc_1p2 = 1;
    y420 = 1;
    dsc_12bpc = 1;
    dsc_10bpc = 1;
    dsc_max_rate = 3;
    max_slice = 5;
    total_chunk_bytes = 11;
[GSM_49352_16843009_2020_1_aa]
    frl_effect_delay = 1000;

[GSM_49352_16843009_2020_1_a9]
    frl_effect_delay = 1000;

#cloudlink board
[HWT_20483_0_2017_20_b7]
    send_avmute_pkg = 0;