# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass simple-register-coalescing,rename-independent-subregs -o - %s | FileCheck %s
--- |
  define amdgpu_kernel void @test0() { ret void }
  define amdgpu_kernel void @test1() { ret void }
  define amdgpu_kernel void @test2() { ret void }
...
---
# In the test below we have two independent def+use pairs of subregister1 which
# can be moved to a new virtual register. The third def of sub1 however is used
# in combination with sub0 and needs to stay with the original vreg.
# CHECK-LABEL: name: test0
# CHECK: S_NOP 0, implicit-def undef %0.sub0
# CHECK: S_NOP 0, implicit-def undef %2.sub1
# CHECK: S_NOP 0, implicit %2.sub1
# CHECK: S_NOP 0, implicit-def undef %1.sub1
# CHECK: S_NOP 0, implicit %1.sub1
# CHECK: S_NOP 0, implicit-def %0.sub1
# CHECK: S_NOP 0, implicit %0
name: test0
registers:
  - { id: 0, class: sgpr_128 }
body: |
  bb.0:
    S_NOP 0, implicit-def undef %0.sub0
    S_NOP 0, implicit-def %0.sub1
    S_NOP 0, implicit %0.sub1
    S_NOP 0, implicit-def %0.sub1
    S_NOP 0, implicit %0.sub1
    S_NOP 0, implicit-def %0.sub1
    S_NOP 0, implicit %0
...
---
# Test for a bug where we would incorrectly query liveness at the instruction
# index in rewriteOperands(). This should pass the verifier afterwards.
# CHECK-LABEL: test1
# CHECK: bb.0
# CHECK: S_NOP 0, implicit-def undef %2.sub2
# CHECK: bb.1
# CHECK: S_NOP 0, implicit-def %2.sub1
# CHECK-NEXT: S_NOP 0, implicit-def %2.sub3
# CHECK-NEXT: S_NOP 0, implicit %2
# CHECK-NEXT: S_NOP 0, implicit-def undef %0.sub0
# CHECK-NEXT: S_NOP 0, implicit %2.sub1
# CHECK-NEXT: S_NOP 0, implicit %0.sub0
# CHECK: bb.2
# CHECK: S_NOP 0, implicit %2.sub
name: test1
registers:
  - { id: 0, class: sgpr_128 }
  - { id: 1, class: sgpr_128 }
body: |
  bb.0:
    S_NOP 0, implicit-def undef %0.sub2
    S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc
    S_BRANCH %bb.2

  bb.1:
    S_NOP 0, implicit-def %0.sub1
    S_NOP 0, implicit-def %0.sub3
    %1 = COPY %0
    S_NOP 0, implicit %1

    S_NOP 0, implicit-def %1.sub0
    S_NOP 0, implicit %1.sub1
    S_NOP 0, implicit %1.sub0

  bb.2:
    S_NOP 0, implicit %0.sub2

...
# In this test, there are two pairs of tied operands
# within the inline asm statement:
# (1) %0.sub0 + %0.sub0 and (2) %0.sub1 + %0.sub1
# Check that renaming (2) does not inadvertently rename (1).
# CHECK-LABEL: name: test2
# CHECK: INLINEASM &"", 32 /* isconvergent attdialect */, 327690 /* regdef:SReg_1_with_sub0 */, def undef %0.sub0, 327690 /* regdef:SReg_1_with_sub0 */, def dead %1.sub1, 2147483657 /* reguse tiedto:$0 */, undef %0.sub0(tied-def 3), 2147549193 /* reguse tiedto:$1 */, %1.sub1(tied-def 5)
name: test2
body: |
  bb.0:
    undef %0.sub0:vreg_64 = IMPLICIT_DEF

  bb.1:
    undef %0.sub1:vreg_64 = V_ALIGNBIT_B32 %0.sub0:vreg_64, %0.sub0:vreg_64, 16, implicit $exec
    INLINEASM &"", 32, 327690, def undef %0.sub0:vreg_64, 327690, def %0.sub1:vreg_64, 2147483657, undef %0.sub0:vreg_64(tied-def 3), 2147549193, %0.sub1:vreg_64(tied-def 5)
    S_BRANCH %bb.1

...