; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IM %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64IM %s define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) nounwind { ; RV32I-LABEL: fold_srem_vec_1: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s4, 8(sp) ; RV32I-NEXT: sw s5, 4(sp) ; RV32I-NEXT: lh s2, 12(a1) ; RV32I-NEXT: lh s3, 8(a1) ; RV32I-NEXT: lh s0, 4(a1) ; RV32I-NEXT: lh a2, 0(a1) ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: addi a1, zero, -124 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: mv s5, a0 ; RV32I-NEXT: addi a1, zero, 98 ; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: addi a1, zero, -1003 ; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: sh a0, 6(s1) ; RV32I-NEXT: sh s0, 4(s1) ; RV32I-NEXT: sh s5, 2(s1) ; RV32I-NEXT: sh s4, 0(s1) ; RV32I-NEXT: lw s5, 4(sp) ; RV32I-NEXT: lw s4, 8(sp) ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; ; RV32IM-LABEL: fold_srem_vec_1: ; RV32IM: # %bb.0: ; RV32IM-NEXT: lh a6, 12(a1) ; RV32IM-NEXT: lh a3, 8(a1) ; RV32IM-NEXT: lh a4, 0(a1) ; RV32IM-NEXT: lh a1, 4(a1) ; RV32IM-NEXT: lui a5, 706409 ; RV32IM-NEXT: addi a5, a5, 389 ; RV32IM-NEXT: mulh a5, a4, a5 ; RV32IM-NEXT: add a5, a5, a4 ; RV32IM-NEXT: srli a2, a5, 31 ; RV32IM-NEXT: srli a5, a5, 6 ; RV32IM-NEXT: add a2, a5, a2 ; RV32IM-NEXT: addi a5, zero, 95 ; RV32IM-NEXT: mul a2, a2, a5 ; RV32IM-NEXT: sub a2, a4, a2 ; RV32IM-NEXT: lui a4, 507375 ; RV32IM-NEXT: addi a4, a4, 1981 ; RV32IM-NEXT: mulh a4, a1, a4 ; RV32IM-NEXT: sub a4, a4, a1 ; RV32IM-NEXT: srli a5, a4, 31 ; RV32IM-NEXT: srli a4, a4, 6 ; RV32IM-NEXT: add a4, a4, a5 ; RV32IM-NEXT: addi a5, zero, -124 ; RV32IM-NEXT: mul a4, a4, a5 ; RV32IM-NEXT: sub a1, a1, a4 ; RV32IM-NEXT: lui a4, 342392 ; RV32IM-NEXT: addi a4, a4, 669 ; RV32IM-NEXT: mulh a4, a3, a4 ; RV32IM-NEXT: srli a5, a4, 31 ; RV32IM-NEXT: srli a4, a4, 5 ; RV32IM-NEXT: add a4, a4, a5 ; RV32IM-NEXT: addi a5, zero, 98 ; RV32IM-NEXT: mul a4, a4, a5 ; RV32IM-NEXT: sub a3, a3, a4 ; RV32IM-NEXT: lui a4, 780943 ; RV32IM-NEXT: addi a4, a4, 1809 ; RV32IM-NEXT: mulh a4, a6, a4 ; RV32IM-NEXT: srli a5, a4, 31 ; RV32IM-NEXT: srli a4, a4, 8 ; RV32IM-NEXT: add a4, a4, a5 ; RV32IM-NEXT: addi a5, zero, -1003 ; RV32IM-NEXT: mul a4, a4, a5 ; RV32IM-NEXT: sub a4, a6, a4 ; RV32IM-NEXT: sh a4, 6(a0) ; RV32IM-NEXT: sh a3, 4(a0) ; RV32IM-NEXT: sh a1, 2(a0) ; RV32IM-NEXT: sh a2, 0(a0) ; RV32IM-NEXT: ret ; ; RV64I-LABEL: fold_srem_vec_1: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -64 ; RV64I-NEXT: sd ra, 56(sp) ; RV64I-NEXT: sd s0, 48(sp) ; RV64I-NEXT: sd s1, 40(sp) ; RV64I-NEXT: sd s2, 32(sp) ; RV64I-NEXT: sd s3, 24(sp) ; RV64I-NEXT: sd s4, 16(sp) ; RV64I-NEXT: sd s5, 8(sp) ; RV64I-NEXT: lh s2, 24(a1) ; RV64I-NEXT: lh s3, 16(a1) ; RV64I-NEXT: lh s0, 8(a1) ; RV64I-NEXT: lh a2, 0(a1) ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: addi a1, zero, -124 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: mv s5, a0 ; RV64I-NEXT: addi a1, zero, 98 ; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: addi a1, zero, -1003 ; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: sh a0, 6(s1) ; RV64I-NEXT: sh s0, 4(s1) ; RV64I-NEXT: sh s5, 2(s1) ; RV64I-NEXT: sh s4, 0(s1) ; RV64I-NEXT: ld s5, 8(sp) ; RV64I-NEXT: ld s4, 16(sp) ; RV64I-NEXT: ld s3, 24(sp) ; RV64I-NEXT: ld s2, 32(sp) ; RV64I-NEXT: ld s1, 40(sp) ; RV64I-NEXT: ld s0, 48(sp) ; RV64I-NEXT: ld ra, 56(sp) ; RV64I-NEXT: addi sp, sp, 64 ; RV64I-NEXT: ret ; ; RV64IM-LABEL: fold_srem_vec_1: ; RV64IM: # %bb.0: ; RV64IM-NEXT: lh a6, 24(a1) ; RV64IM-NEXT: lh a3, 16(a1) ; RV64IM-NEXT: lh a4, 8(a1) ; RV64IM-NEXT: lh a1, 0(a1) ; RV64IM-NEXT: lui a5, 1045903 ; RV64IM-NEXT: addiw a5, a5, -733 ; RV64IM-NEXT: slli a5, a5, 15 ; RV64IM-NEXT: addi a5, a5, 1035 ; RV64IM-NEXT: slli a5, a5, 12 ; RV64IM-NEXT: addi a5, a5, -905 ; RV64IM-NEXT: slli a5, a5, 12 ; RV64IM-NEXT: addi a5, a5, -1767 ; RV64IM-NEXT: mulh a5, a1, a5 ; RV64IM-NEXT: add a5, a5, a1 ; RV64IM-NEXT: srli a2, a5, 63 ; RV64IM-NEXT: srli a5, a5, 6 ; RV64IM-NEXT: add a2, a5, a2 ; RV64IM-NEXT: addi a5, zero, 95 ; RV64IM-NEXT: mul a2, a2, a5 ; RV64IM-NEXT: sub a1, a1, a2 ; RV64IM-NEXT: lui a2, 248 ; RV64IM-NEXT: addiw a2, a2, -1057 ; RV64IM-NEXT: slli a2, a2, 15 ; RV64IM-NEXT: addi a2, a2, -1057 ; RV64IM-NEXT: slli a2, a2, 15 ; RV64IM-NEXT: addi a2, a2, -1057 ; RV64IM-NEXT: slli a2, a2, 13 ; RV64IM-NEXT: addi a2, a2, -265 ; RV64IM-NEXT: mulh a2, a4, a2 ; RV64IM-NEXT: sub a2, a2, a4 ; RV64IM-NEXT: srli a5, a2, 63 ; RV64IM-NEXT: srli a2, a2, 6 ; RV64IM-NEXT: add a2, a2, a5 ; RV64IM-NEXT: addi a5, zero, -124 ; RV64IM-NEXT: mul a2, a2, a5 ; RV64IM-NEXT: sub a2, a4, a2 ; RV64IM-NEXT: lui a4, 2675 ; RV64IM-NEXT: addiw a4, a4, -251 ; RV64IM-NEXT: slli a4, a4, 13 ; RV64IM-NEXT: addi a4, a4, 1839 ; RV64IM-NEXT: slli a4, a4, 13 ; RV64IM-NEXT: addi a4, a4, 167 ; RV64IM-NEXT: slli a4, a4, 13 ; RV64IM-NEXT: addi a4, a4, 1505 ; RV64IM-NEXT: mulh a4, a3, a4 ; RV64IM-NEXT: srli a5, a4, 63 ; RV64IM-NEXT: srli a4, a4, 5 ; RV64IM-NEXT: add a4, a4, a5 ; RV64IM-NEXT: addi a5, zero, 98 ; RV64IM-NEXT: mul a4, a4, a5 ; RV64IM-NEXT: sub a3, a3, a4 ; RV64IM-NEXT: lui a4, 1040212 ; RV64IM-NEXT: addiw a4, a4, 1977 ; RV64IM-NEXT: slli a4, a4, 12 ; RV64IM-NEXT: addi a4, a4, -1907 ; RV64IM-NEXT: slli a4, a4, 12 ; RV64IM-NEXT: addi a4, a4, -453 ; RV64IM-NEXT: slli a4, a4, 12 ; RV64IM-NEXT: addi a4, a4, -1213 ; RV64IM-NEXT: mulh a4, a6, a4 ; RV64IM-NEXT: srli a5, a4, 63 ; RV64IM-NEXT: srli a4, a4, 7 ; RV64IM-NEXT: add a4, a4, a5 ; RV64IM-NEXT: addi a5, zero, -1003 ; RV64IM-NEXT: mul a4, a4, a5 ; RV64IM-NEXT: sub a4, a6, a4 ; RV64IM-NEXT: sh a4, 6(a0) ; RV64IM-NEXT: sh a3, 4(a0) ; RV64IM-NEXT: sh a2, 2(a0) ; RV64IM-NEXT: sh a1, 0(a0) ; RV64IM-NEXT: ret %1 = srem <4 x i16> %x, ret <4 x i16> %1 } define <4 x i16> @fold_srem_vec_2(<4 x i16> %x) nounwind { ; RV32I-LABEL: fold_srem_vec_2: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s4, 8(sp) ; RV32I-NEXT: sw s5, 4(sp) ; RV32I-NEXT: lh s2, 12(a1) ; RV32I-NEXT: lh s3, 8(a1) ; RV32I-NEXT: lh s0, 4(a1) ; RV32I-NEXT: lh a2, 0(a1) ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: mv s5, a0 ; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: sh a0, 6(s1) ; RV32I-NEXT: sh s0, 4(s1) ; RV32I-NEXT: sh s5, 2(s1) ; RV32I-NEXT: sh s4, 0(s1) ; RV32I-NEXT: lw s5, 4(sp) ; RV32I-NEXT: lw s4, 8(sp) ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; ; RV32IM-LABEL: fold_srem_vec_2: ; RV32IM: # %bb.0: ; RV32IM-NEXT: lh a6, 12(a1) ; RV32IM-NEXT: lh a3, 8(a1) ; RV32IM-NEXT: lh a4, 0(a1) ; RV32IM-NEXT: lh a1, 4(a1) ; RV32IM-NEXT: lui a5, 706409 ; RV32IM-NEXT: addi a5, a5, 389 ; RV32IM-NEXT: mulh a2, a4, a5 ; RV32IM-NEXT: add a2, a2, a4 ; RV32IM-NEXT: srli a7, a2, 31 ; RV32IM-NEXT: srli a2, a2, 6 ; RV32IM-NEXT: add a2, a2, a7 ; RV32IM-NEXT: addi a7, zero, 95 ; RV32IM-NEXT: mul a2, a2, a7 ; RV32IM-NEXT: sub t0, a4, a2 ; RV32IM-NEXT: mulh a4, a1, a5 ; RV32IM-NEXT: add a4, a4, a1 ; RV32IM-NEXT: srli a2, a4, 31 ; RV32IM-NEXT: srli a4, a4, 6 ; RV32IM-NEXT: add a2, a4, a2 ; RV32IM-NEXT: mul a2, a2, a7 ; RV32IM-NEXT: sub a1, a1, a2 ; RV32IM-NEXT: mulh a2, a3, a5 ; RV32IM-NEXT: add a2, a2, a3 ; RV32IM-NEXT: srli a4, a2, 31 ; RV32IM-NEXT: srli a2, a2, 6 ; RV32IM-NEXT: add a2, a2, a4 ; RV32IM-NEXT: mul a2, a2, a7 ; RV32IM-NEXT: sub a2, a3, a2 ; RV32IM-NEXT: mulh a3, a6, a5 ; RV32IM-NEXT: add a3, a3, a6 ; RV32IM-NEXT: srli a4, a3, 31 ; RV32IM-NEXT: srli a3, a3, 6 ; RV32IM-NEXT: add a3, a3, a4 ; RV32IM-NEXT: mul a3, a3, a7 ; RV32IM-NEXT: sub a3, a6, a3 ; RV32IM-NEXT: sh a3, 6(a0) ; RV32IM-NEXT: sh a2, 4(a0) ; RV32IM-NEXT: sh a1, 2(a0) ; RV32IM-NEXT: sh t0, 0(a0) ; RV32IM-NEXT: ret ; ; RV64I-LABEL: fold_srem_vec_2: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -64 ; RV64I-NEXT: sd ra, 56(sp) ; RV64I-NEXT: sd s0, 48(sp) ; RV64I-NEXT: sd s1, 40(sp) ; RV64I-NEXT: sd s2, 32(sp) ; RV64I-NEXT: sd s3, 24(sp) ; RV64I-NEXT: sd s4, 16(sp) ; RV64I-NEXT: sd s5, 8(sp) ; RV64I-NEXT: lh s2, 24(a1) ; RV64I-NEXT: lh s3, 16(a1) ; RV64I-NEXT: lh s0, 8(a1) ; RV64I-NEXT: lh a2, 0(a1) ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: mv s5, a0 ; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: sh a0, 6(s1) ; RV64I-NEXT: sh s0, 4(s1) ; RV64I-NEXT: sh s5, 2(s1) ; RV64I-NEXT: sh s4, 0(s1) ; RV64I-NEXT: ld s5, 8(sp) ; RV64I-NEXT: ld s4, 16(sp) ; RV64I-NEXT: ld s3, 24(sp) ; RV64I-NEXT: ld s2, 32(sp) ; RV64I-NEXT: ld s1, 40(sp) ; RV64I-NEXT: ld s0, 48(sp) ; RV64I-NEXT: ld ra, 56(sp) ; RV64I-NEXT: addi sp, sp, 64 ; RV64I-NEXT: ret ; ; RV64IM-LABEL: fold_srem_vec_2: ; RV64IM: # %bb.0: ; RV64IM-NEXT: lh a6, 24(a1) ; RV64IM-NEXT: lh a7, 16(a1) ; RV64IM-NEXT: lh a4, 8(a1) ; RV64IM-NEXT: lh a1, 0(a1) ; RV64IM-NEXT: lui a5, 1045903 ; RV64IM-NEXT: addiw a5, a5, -733 ; RV64IM-NEXT: slli a5, a5, 15 ; RV64IM-NEXT: addi a5, a5, 1035 ; RV64IM-NEXT: slli a5, a5, 12 ; RV64IM-NEXT: addi a5, a5, -905 ; RV64IM-NEXT: slli a5, a5, 12 ; RV64IM-NEXT: addi a5, a5, -1767 ; RV64IM-NEXT: mulh a2, a1, a5 ; RV64IM-NEXT: add a2, a2, a1 ; RV64IM-NEXT: srli a3, a2, 63 ; RV64IM-NEXT: srli a2, a2, 6 ; RV64IM-NEXT: add a2, a2, a3 ; RV64IM-NEXT: addi a3, zero, 95 ; RV64IM-NEXT: mul a2, a2, a3 ; RV64IM-NEXT: sub t0, a1, a2 ; RV64IM-NEXT: mulh a2, a4, a5 ; RV64IM-NEXT: add a2, a2, a4 ; RV64IM-NEXT: srli a1, a2, 63 ; RV64IM-NEXT: srli a2, a2, 6 ; RV64IM-NEXT: add a1, a2, a1 ; RV64IM-NEXT: mul a1, a1, a3 ; RV64IM-NEXT: sub a1, a4, a1 ; RV64IM-NEXT: mulh a2, a7, a5 ; RV64IM-NEXT: add a2, a2, a7 ; RV64IM-NEXT: srli a4, a2, 63 ; RV64IM-NEXT: srli a2, a2, 6 ; RV64IM-NEXT: add a2, a2, a4 ; RV64IM-NEXT: mul a2, a2, a3 ; RV64IM-NEXT: sub a2, a7, a2 ; RV64IM-NEXT: mulh a4, a6, a5 ; RV64IM-NEXT: add a4, a4, a6 ; RV64IM-NEXT: srli a5, a4, 63 ; RV64IM-NEXT: srli a4, a4, 6 ; RV64IM-NEXT: add a4, a4, a5 ; RV64IM-NEXT: mul a3, a4, a3 ; RV64IM-NEXT: sub a3, a6, a3 ; RV64IM-NEXT: sh a3, 6(a0) ; RV64IM-NEXT: sh a2, 4(a0) ; RV64IM-NEXT: sh a1, 2(a0) ; RV64IM-NEXT: sh t0, 0(a0) ; RV64IM-NEXT: ret %1 = srem <4 x i16> %x, ret <4 x i16> %1 } ; Don't fold if we can combine srem with sdiv. define <4 x i16> @combine_srem_sdiv(<4 x i16> %x) nounwind { ; RV32I-LABEL: combine_srem_sdiv: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -48 ; RV32I-NEXT: sw ra, 44(sp) ; RV32I-NEXT: sw s0, 40(sp) ; RV32I-NEXT: sw s1, 36(sp) ; RV32I-NEXT: sw s2, 32(sp) ; RV32I-NEXT: sw s3, 28(sp) ; RV32I-NEXT: sw s4, 24(sp) ; RV32I-NEXT: sw s5, 20(sp) ; RV32I-NEXT: sw s6, 16(sp) ; RV32I-NEXT: sw s7, 12(sp) ; RV32I-NEXT: sw s8, 8(sp) ; RV32I-NEXT: sw s9, 4(sp) ; RV32I-NEXT: lh s2, 0(a1) ; RV32I-NEXT: lh s3, 4(a1) ; RV32I-NEXT: lh s4, 8(a1) ; RV32I-NEXT: lh s1, 12(a1) ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: mv s5, a0 ; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: mv s6, a0 ; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: mv s7, a0 ; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: mv s8, a0 ; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: call __divsi3 ; RV32I-NEXT: mv s9, a0 ; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: call __divsi3 ; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: call __divsi3 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: call __divsi3 ; RV32I-NEXT: add a0, s8, a0 ; RV32I-NEXT: add a1, s7, s1 ; RV32I-NEXT: add a2, s6, s4 ; RV32I-NEXT: add a3, s5, s9 ; RV32I-NEXT: sh a3, 6(s0) ; RV32I-NEXT: sh a2, 4(s0) ; RV32I-NEXT: sh a1, 2(s0) ; RV32I-NEXT: sh a0, 0(s0) ; RV32I-NEXT: lw s9, 4(sp) ; RV32I-NEXT: lw s8, 8(sp) ; RV32I-NEXT: lw s7, 12(sp) ; RV32I-NEXT: lw s6, 16(sp) ; RV32I-NEXT: lw s5, 20(sp) ; RV32I-NEXT: lw s4, 24(sp) ; RV32I-NEXT: lw s3, 28(sp) ; RV32I-NEXT: lw s2, 32(sp) ; RV32I-NEXT: lw s1, 36(sp) ; RV32I-NEXT: lw s0, 40(sp) ; RV32I-NEXT: lw ra, 44(sp) ; RV32I-NEXT: addi sp, sp, 48 ; RV32I-NEXT: ret ; ; RV32IM-LABEL: combine_srem_sdiv: ; RV32IM: # %bb.0: ; RV32IM-NEXT: lh a6, 0(a1) ; RV32IM-NEXT: lh a3, 4(a1) ; RV32IM-NEXT: lh a4, 12(a1) ; RV32IM-NEXT: lh a1, 8(a1) ; RV32IM-NEXT: lui a5, 706409 ; RV32IM-NEXT: addi a5, a5, 389 ; RV32IM-NEXT: mulh a2, a4, a5 ; RV32IM-NEXT: add a2, a2, a4 ; RV32IM-NEXT: srli a7, a2, 31 ; RV32IM-NEXT: srai a2, a2, 6 ; RV32IM-NEXT: add t0, a2, a7 ; RV32IM-NEXT: addi a7, zero, 95 ; RV32IM-NEXT: mul a2, t0, a7 ; RV32IM-NEXT: sub t1, a4, a2 ; RV32IM-NEXT: mulh a4, a1, a5 ; RV32IM-NEXT: add a4, a4, a1 ; RV32IM-NEXT: srli a2, a4, 31 ; RV32IM-NEXT: srai a4, a4, 6 ; RV32IM-NEXT: add a2, a4, a2 ; RV32IM-NEXT: mul a4, a2, a7 ; RV32IM-NEXT: sub t2, a1, a4 ; RV32IM-NEXT: mulh a4, a3, a5 ; RV32IM-NEXT: add a4, a4, a3 ; RV32IM-NEXT: srli a1, a4, 31 ; RV32IM-NEXT: srai a4, a4, 6 ; RV32IM-NEXT: add a1, a4, a1 ; RV32IM-NEXT: mul a4, a1, a7 ; RV32IM-NEXT: sub a3, a3, a4 ; RV32IM-NEXT: mulh a4, a6, a5 ; RV32IM-NEXT: add a4, a4, a6 ; RV32IM-NEXT: srli a5, a4, 31 ; RV32IM-NEXT: srai a4, a4, 6 ; RV32IM-NEXT: add a4, a4, a5 ; RV32IM-NEXT: mul a5, a4, a7 ; RV32IM-NEXT: sub a5, a6, a5 ; RV32IM-NEXT: add a4, a5, a4 ; RV32IM-NEXT: add a1, a3, a1 ; RV32IM-NEXT: add a2, t2, a2 ; RV32IM-NEXT: add a3, t1, t0 ; RV32IM-NEXT: sh a3, 6(a0) ; RV32IM-NEXT: sh a2, 4(a0) ; RV32IM-NEXT: sh a1, 2(a0) ; RV32IM-NEXT: sh a4, 0(a0) ; RV32IM-NEXT: ret ; ; RV64I-LABEL: combine_srem_sdiv: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -96 ; RV64I-NEXT: sd ra, 88(sp) ; RV64I-NEXT: sd s0, 80(sp) ; RV64I-NEXT: sd s1, 72(sp) ; RV64I-NEXT: sd s2, 64(sp) ; RV64I-NEXT: sd s3, 56(sp) ; RV64I-NEXT: sd s4, 48(sp) ; RV64I-NEXT: sd s5, 40(sp) ; RV64I-NEXT: sd s6, 32(sp) ; RV64I-NEXT: sd s7, 24(sp) ; RV64I-NEXT: sd s8, 16(sp) ; RV64I-NEXT: sd s9, 8(sp) ; RV64I-NEXT: lh s2, 0(a1) ; RV64I-NEXT: lh s3, 8(a1) ; RV64I-NEXT: lh s4, 16(a1) ; RV64I-NEXT: lh s1, 24(a1) ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: mv s5, a0 ; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: mv a0, s4 ; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: mv s6, a0 ; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: mv s7, a0 ; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: mv s8, a0 ; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: mv s9, a0 ; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: mv a0, s4 ; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: add a0, s8, a0 ; RV64I-NEXT: add a1, s7, s1 ; RV64I-NEXT: add a2, s6, s4 ; RV64I-NEXT: add a3, s5, s9 ; RV64I-NEXT: sh a3, 6(s0) ; RV64I-NEXT: sh a2, 4(s0) ; RV64I-NEXT: sh a1, 2(s0) ; RV64I-NEXT: sh a0, 0(s0) ; RV64I-NEXT: ld s9, 8(sp) ; RV64I-NEXT: ld s8, 16(sp) ; RV64I-NEXT: ld s7, 24(sp) ; RV64I-NEXT: ld s6, 32(sp) ; RV64I-NEXT: ld s5, 40(sp) ; RV64I-NEXT: ld s4, 48(sp) ; RV64I-NEXT: ld s3, 56(sp) ; RV64I-NEXT: ld s2, 64(sp) ; RV64I-NEXT: ld s1, 72(sp) ; RV64I-NEXT: ld s0, 80(sp) ; RV64I-NEXT: ld ra, 88(sp) ; RV64I-NEXT: addi sp, sp, 96 ; RV64I-NEXT: ret ; ; RV64IM-LABEL: combine_srem_sdiv: ; RV64IM: # %bb.0: ; RV64IM-NEXT: lh a6, 0(a1) ; RV64IM-NEXT: lh a7, 8(a1) ; RV64IM-NEXT: lh a4, 16(a1) ; RV64IM-NEXT: lh a1, 24(a1) ; RV64IM-NEXT: lui a5, 1045903 ; RV64IM-NEXT: addiw a5, a5, -733 ; RV64IM-NEXT: slli a5, a5, 15 ; RV64IM-NEXT: addi a5, a5, 1035 ; RV64IM-NEXT: slli a5, a5, 12 ; RV64IM-NEXT: addi a5, a5, -905 ; RV64IM-NEXT: slli a5, a5, 12 ; RV64IM-NEXT: addi a5, a5, -1767 ; RV64IM-NEXT: mulh a2, a1, a5 ; RV64IM-NEXT: add a2, a2, a1 ; RV64IM-NEXT: srli a3, a2, 63 ; RV64IM-NEXT: srai a2, a2, 6 ; RV64IM-NEXT: add t3, a2, a3 ; RV64IM-NEXT: addi t0, zero, 95 ; RV64IM-NEXT: mul a3, t3, t0 ; RV64IM-NEXT: sub t1, a1, a3 ; RV64IM-NEXT: mulh a3, a4, a5 ; RV64IM-NEXT: add a3, a3, a4 ; RV64IM-NEXT: srli a1, a3, 63 ; RV64IM-NEXT: srai a3, a3, 6 ; RV64IM-NEXT: add a1, a3, a1 ; RV64IM-NEXT: mul a3, a1, t0 ; RV64IM-NEXT: sub t2, a4, a3 ; RV64IM-NEXT: mulh a4, a7, a5 ; RV64IM-NEXT: add a4, a4, a7 ; RV64IM-NEXT: srli a3, a4, 63 ; RV64IM-NEXT: srai a4, a4, 6 ; RV64IM-NEXT: add a3, a4, a3 ; RV64IM-NEXT: mul a4, a3, t0 ; RV64IM-NEXT: sub a4, a7, a4 ; RV64IM-NEXT: mulh a5, a6, a5 ; RV64IM-NEXT: add a5, a5, a6 ; RV64IM-NEXT: srli a2, a5, 63 ; RV64IM-NEXT: srai a5, a5, 6 ; RV64IM-NEXT: add a2, a5, a2 ; RV64IM-NEXT: mul a5, a2, t0 ; RV64IM-NEXT: sub a5, a6, a5 ; RV64IM-NEXT: add a2, a5, a2 ; RV64IM-NEXT: add a3, a4, a3 ; RV64IM-NEXT: add a1, t2, a1 ; RV64IM-NEXT: add a4, t1, t3 ; RV64IM-NEXT: sh a4, 6(a0) ; RV64IM-NEXT: sh a1, 4(a0) ; RV64IM-NEXT: sh a3, 2(a0) ; RV64IM-NEXT: sh a2, 0(a0) ; RV64IM-NEXT: ret %1 = srem <4 x i16> %x, %2 = sdiv <4 x i16> %x, %3 = add <4 x i16> %1, %2 ret <4 x i16> %3 } ; Don't fold for divisors that are a power of two. define <4 x i16> @dont_fold_srem_power_of_two(<4 x i16> %x) nounwind { ; RV32I-LABEL: dont_fold_srem_power_of_two: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: lh a2, 0(a1) ; RV32I-NEXT: lh a0, 12(a1) ; RV32I-NEXT: lh a3, 8(a1) ; RV32I-NEXT: lh a1, 4(a1) ; RV32I-NEXT: srli a4, a2, 26 ; RV32I-NEXT: add a4, a2, a4 ; RV32I-NEXT: lui a6, 16 ; RV32I-NEXT: addi a5, a6, -64 ; RV32I-NEXT: and a4, a4, a5 ; RV32I-NEXT: sub s2, a2, a4 ; RV32I-NEXT: srli a2, a1, 27 ; RV32I-NEXT: add a2, a1, a2 ; RV32I-NEXT: addi a4, a6, -32 ; RV32I-NEXT: and a2, a2, a4 ; RV32I-NEXT: sub s3, a1, a2 ; RV32I-NEXT: srli a1, a3, 29 ; RV32I-NEXT: add a1, a3, a1 ; RV32I-NEXT: addi a2, a6, -8 ; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: sub s1, a3, a1 ; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: sh a0, 6(s0) ; RV32I-NEXT: sh s1, 4(s0) ; RV32I-NEXT: sh s3, 2(s0) ; RV32I-NEXT: sh s2, 0(s0) ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; ; RV32IM-LABEL: dont_fold_srem_power_of_two: ; RV32IM: # %bb.0: ; RV32IM-NEXT: lh a6, 8(a1) ; RV32IM-NEXT: lh a3, 4(a1) ; RV32IM-NEXT: lh a4, 12(a1) ; RV32IM-NEXT: lh a1, 0(a1) ; RV32IM-NEXT: lui a5, 706409 ; RV32IM-NEXT: addi a5, a5, 389 ; RV32IM-NEXT: mulh a5, a4, a5 ; RV32IM-NEXT: add a5, a5, a4 ; RV32IM-NEXT: srli a2, a5, 31 ; RV32IM-NEXT: srli a5, a5, 6 ; RV32IM-NEXT: add a2, a5, a2 ; RV32IM-NEXT: addi a5, zero, 95 ; RV32IM-NEXT: mul a2, a2, a5 ; RV32IM-NEXT: sub a7, a4, a2 ; RV32IM-NEXT: srli a4, a1, 26 ; RV32IM-NEXT: add a4, a1, a4 ; RV32IM-NEXT: lui a5, 16 ; RV32IM-NEXT: addi a2, a5, -64 ; RV32IM-NEXT: and a2, a4, a2 ; RV32IM-NEXT: sub a1, a1, a2 ; RV32IM-NEXT: srli a2, a3, 27 ; RV32IM-NEXT: add a2, a3, a2 ; RV32IM-NEXT: addi a4, a5, -32 ; RV32IM-NEXT: and a2, a2, a4 ; RV32IM-NEXT: sub a2, a3, a2 ; RV32IM-NEXT: srli a3, a6, 29 ; RV32IM-NEXT: add a3, a6, a3 ; RV32IM-NEXT: addi a4, a5, -8 ; RV32IM-NEXT: and a3, a3, a4 ; RV32IM-NEXT: sub a3, a6, a3 ; RV32IM-NEXT: sh a3, 4(a0) ; RV32IM-NEXT: sh a2, 2(a0) ; RV32IM-NEXT: sh a1, 0(a0) ; RV32IM-NEXT: sh a7, 6(a0) ; RV32IM-NEXT: ret ; ; RV64I-LABEL: dont_fold_srem_power_of_two: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: lh a2, 0(a1) ; RV64I-NEXT: lh a0, 24(a1) ; RV64I-NEXT: lh a3, 16(a1) ; RV64I-NEXT: lh a1, 8(a1) ; RV64I-NEXT: srli a4, a2, 58 ; RV64I-NEXT: add a4, a2, a4 ; RV64I-NEXT: lui a6, 16 ; RV64I-NEXT: addiw a5, a6, -64 ; RV64I-NEXT: and a4, a4, a5 ; RV64I-NEXT: sub s2, a2, a4 ; RV64I-NEXT: srli a2, a1, 59 ; RV64I-NEXT: add a2, a1, a2 ; RV64I-NEXT: addiw a4, a6, -32 ; RV64I-NEXT: and a2, a2, a4 ; RV64I-NEXT: sub s3, a1, a2 ; RV64I-NEXT: srli a1, a3, 61 ; RV64I-NEXT: add a1, a3, a1 ; RV64I-NEXT: addiw a2, a6, -8 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: sub s1, a3, a1 ; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: sh a0, 6(s0) ; RV64I-NEXT: sh s1, 4(s0) ; RV64I-NEXT: sh s3, 2(s0) ; RV64I-NEXT: sh s2, 0(s0) ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; ; RV64IM-LABEL: dont_fold_srem_power_of_two: ; RV64IM: # %bb.0: ; RV64IM-NEXT: lh a6, 16(a1) ; RV64IM-NEXT: lh a3, 8(a1) ; RV64IM-NEXT: lh a4, 0(a1) ; RV64IM-NEXT: lh a1, 24(a1) ; RV64IM-NEXT: lui a5, 1045903 ; RV64IM-NEXT: addiw a5, a5, -733 ; RV64IM-NEXT: slli a5, a5, 15 ; RV64IM-NEXT: addi a5, a5, 1035 ; RV64IM-NEXT: slli a5, a5, 12 ; RV64IM-NEXT: addi a5, a5, -905 ; RV64IM-NEXT: slli a5, a5, 12 ; RV64IM-NEXT: addi a5, a5, -1767 ; RV64IM-NEXT: mulh a5, a1, a5 ; RV64IM-NEXT: add a5, a5, a1 ; RV64IM-NEXT: srli a2, a5, 63 ; RV64IM-NEXT: srli a5, a5, 6 ; RV64IM-NEXT: add a2, a5, a2 ; RV64IM-NEXT: addi a5, zero, 95 ; RV64IM-NEXT: mul a2, a2, a5 ; RV64IM-NEXT: sub a7, a1, a2 ; RV64IM-NEXT: srli a2, a4, 58 ; RV64IM-NEXT: add a2, a4, a2 ; RV64IM-NEXT: lui a5, 16 ; RV64IM-NEXT: addiw a1, a5, -64 ; RV64IM-NEXT: and a1, a2, a1 ; RV64IM-NEXT: sub a1, a4, a1 ; RV64IM-NEXT: srli a2, a3, 59 ; RV64IM-NEXT: add a2, a3, a2 ; RV64IM-NEXT: addiw a4, a5, -32 ; RV64IM-NEXT: and a2, a2, a4 ; RV64IM-NEXT: sub a2, a3, a2 ; RV64IM-NEXT: srli a3, a6, 61 ; RV64IM-NEXT: add a3, a6, a3 ; RV64IM-NEXT: addiw a4, a5, -8 ; RV64IM-NEXT: and a3, a3, a4 ; RV64IM-NEXT: sub a3, a6, a3 ; RV64IM-NEXT: sh a3, 4(a0) ; RV64IM-NEXT: sh a2, 2(a0) ; RV64IM-NEXT: sh a1, 0(a0) ; RV64IM-NEXT: sh a7, 6(a0) ; RV64IM-NEXT: ret %1 = srem <4 x i16> %x, ret <4 x i16> %1 } ; Don't fold if the divisor is one. define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) nounwind { ; RV32I-LABEL: dont_fold_srem_one: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: lh s2, 12(a1) ; RV32I-NEXT: lh s1, 8(a1) ; RV32I-NEXT: lh a2, 4(a1) ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: addi a1, zero, 654 ; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: addi a1, zero, 23 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lui a0, 1 ; RV32I-NEXT: addi a1, a0, 1327 ; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: sh zero, 0(s0) ; RV32I-NEXT: sh a0, 6(s0) ; RV32I-NEXT: sh s1, 4(s0) ; RV32I-NEXT: sh s3, 2(s0) ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; ; RV32IM-LABEL: dont_fold_srem_one: ; RV32IM: # %bb.0: ; RV32IM-NEXT: lh a2, 12(a1) ; RV32IM-NEXT: lh a3, 4(a1) ; RV32IM-NEXT: lh a1, 8(a1) ; RV32IM-NEXT: lui a4, 820904 ; RV32IM-NEXT: addi a4, a4, -1903 ; RV32IM-NEXT: mulh a4, a3, a4 ; RV32IM-NEXT: add a4, a4, a3 ; RV32IM-NEXT: srli a5, a4, 31 ; RV32IM-NEXT: srli a4, a4, 9 ; RV32IM-NEXT: add a4, a4, a5 ; RV32IM-NEXT: addi a5, zero, 654 ; RV32IM-NEXT: mul a4, a4, a5 ; RV32IM-NEXT: sub a3, a3, a4 ; RV32IM-NEXT: lui a4, 729444 ; RV32IM-NEXT: addi a4, a4, 713 ; RV32IM-NEXT: mulh a4, a1, a4 ; RV32IM-NEXT: add a4, a4, a1 ; RV32IM-NEXT: srli a5, a4, 31 ; RV32IM-NEXT: srli a4, a4, 4 ; RV32IM-NEXT: add a4, a4, a5 ; RV32IM-NEXT: addi a5, zero, 23 ; RV32IM-NEXT: mul a4, a4, a5 ; RV32IM-NEXT: sub a1, a1, a4 ; RV32IM-NEXT: lui a4, 395996 ; RV32IM-NEXT: addi a4, a4, -2009 ; RV32IM-NEXT: mulh a4, a2, a4 ; RV32IM-NEXT: srli a5, a4, 31 ; RV32IM-NEXT: srli a4, a4, 11 ; RV32IM-NEXT: add a4, a4, a5 ; RV32IM-NEXT: lui a5, 1 ; RV32IM-NEXT: addi a5, a5, 1327 ; RV32IM-NEXT: mul a4, a4, a5 ; RV32IM-NEXT: sub a2, a2, a4 ; RV32IM-NEXT: sh zero, 0(a0) ; RV32IM-NEXT: sh a2, 6(a0) ; RV32IM-NEXT: sh a1, 4(a0) ; RV32IM-NEXT: sh a3, 2(a0) ; RV32IM-NEXT: ret ; ; RV64I-LABEL: dont_fold_srem_one: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: lh s2, 24(a1) ; RV64I-NEXT: lh s1, 16(a1) ; RV64I-NEXT: lh a2, 8(a1) ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: addi a1, zero, 654 ; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: addi a1, zero, 23 ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lui a0, 1 ; RV64I-NEXT: addiw a1, a0, 1327 ; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: sh zero, 0(s0) ; RV64I-NEXT: sh a0, 6(s0) ; RV64I-NEXT: sh s1, 4(s0) ; RV64I-NEXT: sh s3, 2(s0) ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; ; RV64IM-LABEL: dont_fold_srem_one: ; RV64IM: # %bb.0: ; RV64IM-NEXT: lh a2, 24(a1) ; RV64IM-NEXT: lh a3, 8(a1) ; RV64IM-NEXT: lh a1, 16(a1) ; RV64IM-NEXT: lui a4, 1043590 ; RV64IM-NEXT: addiw a4, a4, -1781 ; RV64IM-NEXT: slli a4, a4, 13 ; RV64IM-NEXT: addi a4, a4, 1069 ; RV64IM-NEXT: slli a4, a4, 12 ; RV64IM-NEXT: addi a4, a4, -1959 ; RV64IM-NEXT: slli a4, a4, 13 ; RV64IM-NEXT: addi a4, a4, 357 ; RV64IM-NEXT: mulh a4, a1, a4 ; RV64IM-NEXT: add a4, a4, a1 ; RV64IM-NEXT: srli a5, a4, 63 ; RV64IM-NEXT: srli a4, a4, 4 ; RV64IM-NEXT: add a4, a4, a5 ; RV64IM-NEXT: addi a5, zero, 23 ; RV64IM-NEXT: mul a4, a4, a5 ; RV64IM-NEXT: sub a1, a1, a4 ; RV64IM-NEXT: lui a4, 6413 ; RV64IM-NEXT: addiw a4, a4, 1265 ; RV64IM-NEXT: slli a4, a4, 13 ; RV64IM-NEXT: addi a4, a4, 1027 ; RV64IM-NEXT: slli a4, a4, 13 ; RV64IM-NEXT: addi a4, a4, 1077 ; RV64IM-NEXT: slli a4, a4, 12 ; RV64IM-NEXT: addi a4, a4, 965 ; RV64IM-NEXT: mulh a4, a3, a4 ; RV64IM-NEXT: srli a5, a4, 63 ; RV64IM-NEXT: srli a4, a4, 8 ; RV64IM-NEXT: add a4, a4, a5 ; RV64IM-NEXT: addi a5, zero, 654 ; RV64IM-NEXT: mul a4, a4, a5 ; RV64IM-NEXT: sub a3, a3, a4 ; RV64IM-NEXT: lui a4, 12375 ; RV64IM-NEXT: addiw a4, a4, -575 ; RV64IM-NEXT: slli a4, a4, 12 ; RV64IM-NEXT: addi a4, a4, 883 ; RV64IM-NEXT: slli a4, a4, 13 ; RV64IM-NEXT: addi a4, a4, -431 ; RV64IM-NEXT: slli a4, a4, 12 ; RV64IM-NEXT: addi a4, a4, 1959 ; RV64IM-NEXT: mulh a4, a2, a4 ; RV64IM-NEXT: srli a5, a4, 63 ; RV64IM-NEXT: srli a4, a4, 11 ; RV64IM-NEXT: add a4, a4, a5 ; RV64IM-NEXT: lui a5, 1 ; RV64IM-NEXT: addiw a5, a5, 1327 ; RV64IM-NEXT: mul a4, a4, a5 ; RV64IM-NEXT: sub a2, a2, a4 ; RV64IM-NEXT: sh zero, 0(a0) ; RV64IM-NEXT: sh a2, 6(a0) ; RV64IM-NEXT: sh a3, 2(a0) ; RV64IM-NEXT: sh a1, 4(a0) ; RV64IM-NEXT: ret %1 = srem <4 x i16> %x, ret <4 x i16> %1 } ; Don't fold if the divisor is 2^15. define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) nounwind { ; RV32I-LABEL: dont_fold_urem_i16_smax: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: lh a2, 4(a1) ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: lh s2, 12(a1) ; RV32I-NEXT: lh a0, 8(a1) ; RV32I-NEXT: srli a1, a2, 17 ; RV32I-NEXT: add a1, a2, a1 ; RV32I-NEXT: lui a3, 8 ; RV32I-NEXT: and a1, a1, a3 ; RV32I-NEXT: sub s3, a2, a1 ; RV32I-NEXT: addi a1, zero, 23 ; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lui a0, 1 ; RV32I-NEXT: addi a1, a0, 1327 ; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: sh zero, 0(s0) ; RV32I-NEXT: sh a0, 6(s0) ; RV32I-NEXT: sh s1, 4(s0) ; RV32I-NEXT: sh s3, 2(s0) ; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; ; RV32IM-LABEL: dont_fold_urem_i16_smax: ; RV32IM: # %bb.0: ; RV32IM-NEXT: lh a2, 4(a1) ; RV32IM-NEXT: lh a3, 8(a1) ; RV32IM-NEXT: lh a1, 12(a1) ; RV32IM-NEXT: lui a4, 729444 ; RV32IM-NEXT: addi a4, a4, 713 ; RV32IM-NEXT: mulh a4, a3, a4 ; RV32IM-NEXT: add a4, a4, a3 ; RV32IM-NEXT: srli a5, a4, 31 ; RV32IM-NEXT: srli a4, a4, 4 ; RV32IM-NEXT: add a4, a4, a5 ; RV32IM-NEXT: addi a5, zero, 23 ; RV32IM-NEXT: mul a4, a4, a5 ; RV32IM-NEXT: sub a3, a3, a4 ; RV32IM-NEXT: lui a4, 395996 ; RV32IM-NEXT: addi a4, a4, -2009 ; RV32IM-NEXT: mulh a4, a1, a4 ; RV32IM-NEXT: srli a5, a4, 31 ; RV32IM-NEXT: srli a4, a4, 11 ; RV32IM-NEXT: add a4, a4, a5 ; RV32IM-NEXT: lui a5, 1 ; RV32IM-NEXT: addi a5, a5, 1327 ; RV32IM-NEXT: mul a4, a4, a5 ; RV32IM-NEXT: sub a1, a1, a4 ; RV32IM-NEXT: srli a4, a2, 17 ; RV32IM-NEXT: add a4, a2, a4 ; RV32IM-NEXT: lui a5, 8 ; RV32IM-NEXT: and a4, a4, a5 ; RV32IM-NEXT: sub a2, a2, a4 ; RV32IM-NEXT: sh zero, 0(a0) ; RV32IM-NEXT: sh a2, 2(a0) ; RV32IM-NEXT: sh a1, 6(a0) ; RV32IM-NEXT: sh a3, 4(a0) ; RV32IM-NEXT: ret ; ; RV64I-LABEL: dont_fold_urem_i16_smax: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: lh a2, 8(a1) ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: lh s2, 24(a1) ; RV64I-NEXT: lh a0, 16(a1) ; RV64I-NEXT: srli a1, a2, 49 ; RV64I-NEXT: add a1, a2, a1 ; RV64I-NEXT: lui a3, 8 ; RV64I-NEXT: and a1, a1, a3 ; RV64I-NEXT: sub s3, a2, a1 ; RV64I-NEXT: addi a1, zero, 23 ; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lui a0, 1 ; RV64I-NEXT: addiw a1, a0, 1327 ; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: sh zero, 0(s0) ; RV64I-NEXT: sh a0, 6(s0) ; RV64I-NEXT: sh s1, 4(s0) ; RV64I-NEXT: sh s3, 2(s0) ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; ; RV64IM-LABEL: dont_fold_urem_i16_smax: ; RV64IM: # %bb.0: ; RV64IM-NEXT: lh a2, 8(a1) ; RV64IM-NEXT: lh a3, 24(a1) ; RV64IM-NEXT: lh a1, 16(a1) ; RV64IM-NEXT: lui a4, 1043590 ; RV64IM-NEXT: addiw a4, a4, -1781 ; RV64IM-NEXT: slli a4, a4, 13 ; RV64IM-NEXT: addi a4, a4, 1069 ; RV64IM-NEXT: slli a4, a4, 12 ; RV64IM-NEXT: addi a4, a4, -1959 ; RV64IM-NEXT: slli a4, a4, 13 ; RV64IM-NEXT: addi a4, a4, 357 ; RV64IM-NEXT: mulh a4, a1, a4 ; RV64IM-NEXT: add a4, a4, a1 ; RV64IM-NEXT: srli a5, a4, 63 ; RV64IM-NEXT: srli a4, a4, 4 ; RV64IM-NEXT: add a4, a4, a5 ; RV64IM-NEXT: addi a5, zero, 23 ; RV64IM-NEXT: mul a4, a4, a5 ; RV64IM-NEXT: sub a1, a1, a4 ; RV64IM-NEXT: lui a4, 12375 ; RV64IM-NEXT: addiw a4, a4, -575 ; RV64IM-NEXT: slli a4, a4, 12 ; RV64IM-NEXT: addi a4, a4, 883 ; RV64IM-NEXT: slli a4, a4, 13 ; RV64IM-NEXT: addi a4, a4, -431 ; RV64IM-NEXT: slli a4, a4, 12 ; RV64IM-NEXT: addi a4, a4, 1959 ; RV64IM-NEXT: mulh a4, a3, a4 ; RV64IM-NEXT: srli a5, a4, 63 ; RV64IM-NEXT: srli a4, a4, 11 ; RV64IM-NEXT: add a4, a4, a5 ; RV64IM-NEXT: lui a5, 1 ; RV64IM-NEXT: addiw a5, a5, 1327 ; RV64IM-NEXT: mul a4, a4, a5 ; RV64IM-NEXT: sub a3, a3, a4 ; RV64IM-NEXT: srli a4, a2, 49 ; RV64IM-NEXT: add a4, a2, a4 ; RV64IM-NEXT: lui a5, 8 ; RV64IM-NEXT: and a4, a4, a5 ; RV64IM-NEXT: sub a2, a2, a4 ; RV64IM-NEXT: sh zero, 0(a0) ; RV64IM-NEXT: sh a2, 2(a0) ; RV64IM-NEXT: sh a3, 6(a0) ; RV64IM-NEXT: sh a1, 4(a0) ; RV64IM-NEXT: ret %1 = srem <4 x i16> %x, ret <4 x i16> %1 } ; Don't fold i64 srem. define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) nounwind { ; RV32I-LABEL: dont_fold_srem_i64: ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -48 ; RV32I-NEXT: sw ra, 44(sp) ; RV32I-NEXT: sw s0, 40(sp) ; RV32I-NEXT: sw s1, 36(sp) ; RV32I-NEXT: sw s2, 32(sp) ; RV32I-NEXT: sw s3, 28(sp) ; RV32I-NEXT: sw s4, 24(sp) ; RV32I-NEXT: sw s5, 20(sp) ; RV32I-NEXT: sw s6, 16(sp) ; RV32I-NEXT: sw s7, 12(sp) ; RV32I-NEXT: sw s8, 8(sp) ; RV32I-NEXT: sw s9, 4(sp) ; RV32I-NEXT: lw s2, 24(a1) ; RV32I-NEXT: lw s3, 28(a1) ; RV32I-NEXT: lw s4, 16(a1) ; RV32I-NEXT: lw s5, 20(a1) ; RV32I-NEXT: lw s6, 8(a1) ; RV32I-NEXT: lw s1, 12(a1) ; RV32I-NEXT: lw a3, 0(a1) ; RV32I-NEXT: lw a1, 4(a1) ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: addi a2, zero, 1 ; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: call __moddi3 ; RV32I-NEXT: mv s7, a0 ; RV32I-NEXT: mv s8, a1 ; RV32I-NEXT: addi a2, zero, 654 ; RV32I-NEXT: mv a0, s6 ; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: call __moddi3 ; RV32I-NEXT: mv s6, a0 ; RV32I-NEXT: mv s9, a1 ; RV32I-NEXT: addi a2, zero, 23 ; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: mv a1, s5 ; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: call __moddi3 ; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: lui a0, 1 ; RV32I-NEXT: addi a2, a0, 1327 ; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: call __moddi3 ; RV32I-NEXT: sw a1, 28(s0) ; RV32I-NEXT: sw a0, 24(s0) ; RV32I-NEXT: sw s1, 20(s0) ; RV32I-NEXT: sw s4, 16(s0) ; RV32I-NEXT: sw s9, 12(s0) ; RV32I-NEXT: sw s6, 8(s0) ; RV32I-NEXT: sw s8, 4(s0) ; RV32I-NEXT: sw s7, 0(s0) ; RV32I-NEXT: lw s9, 4(sp) ; RV32I-NEXT: lw s8, 8(sp) ; RV32I-NEXT: lw s7, 12(sp) ; RV32I-NEXT: lw s6, 16(sp) ; RV32I-NEXT: lw s5, 20(sp) ; RV32I-NEXT: lw s4, 24(sp) ; RV32I-NEXT: lw s3, 28(sp) ; RV32I-NEXT: lw s2, 32(sp) ; RV32I-NEXT: lw s1, 36(sp) ; RV32I-NEXT: lw s0, 40(sp) ; RV32I-NEXT: lw ra, 44(sp) ; RV32I-NEXT: addi sp, sp, 48 ; RV32I-NEXT: ret ; ; RV32IM-LABEL: dont_fold_srem_i64: ; RV32IM: # %bb.0: ; RV32IM-NEXT: addi sp, sp, -48 ; RV32IM-NEXT: sw ra, 44(sp) ; RV32IM-NEXT: sw s0, 40(sp) ; RV32IM-NEXT: sw s1, 36(sp) ; RV32IM-NEXT: sw s2, 32(sp) ; RV32IM-NEXT: sw s3, 28(sp) ; RV32IM-NEXT: sw s4, 24(sp) ; RV32IM-NEXT: sw s5, 20(sp) ; RV32IM-NEXT: sw s6, 16(sp) ; RV32IM-NEXT: sw s7, 12(sp) ; RV32IM-NEXT: sw s8, 8(sp) ; RV32IM-NEXT: sw s9, 4(sp) ; RV32IM-NEXT: lw s2, 24(a1) ; RV32IM-NEXT: lw s3, 28(a1) ; RV32IM-NEXT: lw s4, 16(a1) ; RV32IM-NEXT: lw s5, 20(a1) ; RV32IM-NEXT: lw s6, 8(a1) ; RV32IM-NEXT: lw s1, 12(a1) ; RV32IM-NEXT: lw a3, 0(a1) ; RV32IM-NEXT: lw a1, 4(a1) ; RV32IM-NEXT: mv s0, a0 ; RV32IM-NEXT: addi a2, zero, 1 ; RV32IM-NEXT: mv a0, a3 ; RV32IM-NEXT: mv a3, zero ; RV32IM-NEXT: call __moddi3 ; RV32IM-NEXT: mv s7, a0 ; RV32IM-NEXT: mv s8, a1 ; RV32IM-NEXT: addi a2, zero, 654 ; RV32IM-NEXT: mv a0, s6 ; RV32IM-NEXT: mv a1, s1 ; RV32IM-NEXT: mv a3, zero ; RV32IM-NEXT: call __moddi3 ; RV32IM-NEXT: mv s6, a0 ; RV32IM-NEXT: mv s9, a1 ; RV32IM-NEXT: addi a2, zero, 23 ; RV32IM-NEXT: mv a0, s4 ; RV32IM-NEXT: mv a1, s5 ; RV32IM-NEXT: mv a3, zero ; RV32IM-NEXT: call __moddi3 ; RV32IM-NEXT: mv s4, a0 ; RV32IM-NEXT: mv s1, a1 ; RV32IM-NEXT: lui a0, 1 ; RV32IM-NEXT: addi a2, a0, 1327 ; RV32IM-NEXT: mv a0, s2 ; RV32IM-NEXT: mv a1, s3 ; RV32IM-NEXT: mv a3, zero ; RV32IM-NEXT: call __moddi3 ; RV32IM-NEXT: sw a1, 28(s0) ; RV32IM-NEXT: sw a0, 24(s0) ; RV32IM-NEXT: sw s1, 20(s0) ; RV32IM-NEXT: sw s4, 16(s0) ; RV32IM-NEXT: sw s9, 12(s0) ; RV32IM-NEXT: sw s6, 8(s0) ; RV32IM-NEXT: sw s8, 4(s0) ; RV32IM-NEXT: sw s7, 0(s0) ; RV32IM-NEXT: lw s9, 4(sp) ; RV32IM-NEXT: lw s8, 8(sp) ; RV32IM-NEXT: lw s7, 12(sp) ; RV32IM-NEXT: lw s6, 16(sp) ; RV32IM-NEXT: lw s5, 20(sp) ; RV32IM-NEXT: lw s4, 24(sp) ; RV32IM-NEXT: lw s3, 28(sp) ; RV32IM-NEXT: lw s2, 32(sp) ; RV32IM-NEXT: lw s1, 36(sp) ; RV32IM-NEXT: lw s0, 40(sp) ; RV32IM-NEXT: lw ra, 44(sp) ; RV32IM-NEXT: addi sp, sp, 48 ; RV32IM-NEXT: ret ; ; RV64I-LABEL: dont_fold_srem_i64: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: ld s2, 24(a1) ; RV64I-NEXT: ld s1, 16(a1) ; RV64I-NEXT: ld a2, 8(a1) ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: addi a1, zero, 654 ; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: addi a1, zero, 23 ; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lui a0, 1 ; RV64I-NEXT: addiw a1, a0, 1327 ; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: sd zero, 0(s0) ; RV64I-NEXT: sd a0, 24(s0) ; RV64I-NEXT: sd s1, 16(s0) ; RV64I-NEXT: sd s3, 8(s0) ; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret ; ; RV64IM-LABEL: dont_fold_srem_i64: ; RV64IM: # %bb.0: ; RV64IM-NEXT: ld a2, 24(a1) ; RV64IM-NEXT: ld a3, 8(a1) ; RV64IM-NEXT: ld a1, 16(a1) ; RV64IM-NEXT: lui a4, 1043590 ; RV64IM-NEXT: addiw a4, a4, -1781 ; RV64IM-NEXT: slli a4, a4, 13 ; RV64IM-NEXT: addi a4, a4, 1069 ; RV64IM-NEXT: slli a4, a4, 12 ; RV64IM-NEXT: addi a4, a4, -1959 ; RV64IM-NEXT: slli a4, a4, 13 ; RV64IM-NEXT: addi a4, a4, 357 ; RV64IM-NEXT: mulh a4, a1, a4 ; RV64IM-NEXT: add a4, a4, a1 ; RV64IM-NEXT: srli a5, a4, 63 ; RV64IM-NEXT: srai a4, a4, 4 ; RV64IM-NEXT: add a4, a4, a5 ; RV64IM-NEXT: addi a5, zero, 23 ; RV64IM-NEXT: mul a4, a4, a5 ; RV64IM-NEXT: sub a1, a1, a4 ; RV64IM-NEXT: lui a4, 6413 ; RV64IM-NEXT: addiw a4, a4, 1265 ; RV64IM-NEXT: slli a4, a4, 13 ; RV64IM-NEXT: addi a4, a4, 1027 ; RV64IM-NEXT: slli a4, a4, 13 ; RV64IM-NEXT: addi a4, a4, 1077 ; RV64IM-NEXT: slli a4, a4, 12 ; RV64IM-NEXT: addi a4, a4, 965 ; RV64IM-NEXT: mulh a4, a3, a4 ; RV64IM-NEXT: srli a5, a4, 63 ; RV64IM-NEXT: srai a4, a4, 8 ; RV64IM-NEXT: add a4, a4, a5 ; RV64IM-NEXT: addi a5, zero, 654 ; RV64IM-NEXT: mul a4, a4, a5 ; RV64IM-NEXT: sub a3, a3, a4 ; RV64IM-NEXT: lui a4, 12375 ; RV64IM-NEXT: addiw a4, a4, -575 ; RV64IM-NEXT: slli a4, a4, 12 ; RV64IM-NEXT: addi a4, a4, 883 ; RV64IM-NEXT: slli a4, a4, 13 ; RV64IM-NEXT: addi a4, a4, -431 ; RV64IM-NEXT: slli a4, a4, 12 ; RV64IM-NEXT: addi a4, a4, 1959 ; RV64IM-NEXT: mulh a4, a2, a4 ; RV64IM-NEXT: srli a5, a4, 63 ; RV64IM-NEXT: srai a4, a4, 11 ; RV64IM-NEXT: add a4, a4, a5 ; RV64IM-NEXT: lui a5, 1 ; RV64IM-NEXT: addiw a5, a5, 1327 ; RV64IM-NEXT: mul a4, a4, a5 ; RV64IM-NEXT: sub a2, a2, a4 ; RV64IM-NEXT: sd zero, 0(a0) ; RV64IM-NEXT: sd a2, 24(a0) ; RV64IM-NEXT: sd a3, 8(a0) ; RV64IM-NEXT: sd a1, 16(a0) ; RV64IM-NEXT: ret %1 = srem <4 x i64> %x, ret <4 x i64> %1 }