/*
 * Copyright (c) Hisilicon Technologies Co., Ltd. 2014-2020. All rights reserved.
 * Description: cpu ids code
 * Author: SmartMedia_BSP
 * Create: 2014-06-04
 */

#ifndef CPUIDSH
#define CPUIDSH

#define RESERVED13                   (932610816LL)
#define RESERVED13_C                 (932610832LL)
#define RESERVED13_D                 (3272147200LL)
#define RESERVED13_MASK              (0xFFFFFFFFFFLL)

#define RESERVED9                  (932610817LL)
#define RESERVED9_C               (932610833LL)
#define RESERVED9_D            (3272147201LL)
#define RESERVED9_MASK             (0xFFFFFFFFFFLL)

#ifdef CONFIG_SOCT_SLS_B
#define RESERVED19_B_SYSID          (0xC3020200L)
#define RESERVED19_B              (RESERVED19_B_SYSID | (0x1LL << 32))
#elif defined(CONFIG_SOCT_SLS_C)
#define RESERVED19_C_SYSID          (0x19060812L)
#define RESERVED19_C              (RESERVED19_C_SYSID | (0x1LL << 32))
#define HI3751V811_C_SYSID          (0x19060812L)
#define HI3751V811_C                (HI3751V811_C_SYSID | (0x1LL << 32))
#else
#define RESERVED19_SYSID            (0x19060810L)
#define RESERVED19                (RESERVED19_SYSID | (0x1LL << 32))
#endif


#define RESERVED5_B_SYSID            (0xc3030100L)
#define RESERVED5_B                (RESERVED5_B_SYSID | (0x1LL << 32))

#define T9_SYSID_MASK            (0xFFFFFFFFL)
#define T9_MASK                (T9_SYSID_MASK | (0xFLL << 32))

/* The support device every chip platform */
#define DEV_HLNFC_AUTO     0x01
#define DEV_HLNFC301       0x02
#define DEV_HLNFC504       0x03
#define DEV_HLNFC610       0x04
#define DEV_HLFMC100       0x05
#define DEV_HLNFC_MASK     0x0F

#define DEV_EMMC_AUTO      0x10
#define DEV_EMMCV100       0x20
#define DEV_EMMCV200       0x20
#define DEV_EMMC_MASK      0xF0

#define DEV_HLSFC_AUTO     0x100
#define DEV_HLSFC300       0x200
#define DEV_HLSFC350       0x300
#define DEV_NOR_HLFMC100   0x500
#define DEV_HLSFC_MASK     0xF00

/* bootstrap type */
#define SELF_BOOT_TYPE_NONE           (0)  /* boot type: NONE SELF BOOT */
#define SELF_BOOT_TYPE_UART           (1)  /* boot type: UART */
#define SELF_BOOT_TYPE_USBDEV         (2)  /* boot type: USBDEV */
#define SELF_BOOT_TYPE_USBHOST        (3)  /* boot type: USBHOST */

/* chipset ca type */
#define CHIPSET_CATYPE_INVALID        (-1) /* chipset catype: invalid type */
#define CHIPSET_CATYPE_NORMAL         (0)  /* chipset catype: NORMAL */
#define CHIPSET_CATYPE_CA             (1)  /* chipset catype: CA */

/* board type */
#define BOARD_TYPE_0            0x1
#define BOARD_TYPE_1            0x2
#define BOARD_TYPE_2            0x3
#define BOARD_TYPE_RESERVED     0x10
#define BOARD_TYPE_INVALID      0x11

#endif /* CPUIDSH */