/*
 * Copyright (c) Hisilicon Technologies Co., Ltd.. 2021-2021. All rights reserved.
 * Description: pwm driver for reserved5/reserved2 chip.
 * Author:
 * Create: 2021-05-12
 * Note:
 */

/********************************************************************************************/
/* Includes                                                                                 */
/********************************************************************************************/
#include "osal_ext.h"

#include "pwm_common.h"
#include "pwm_v2.h"

/********************************************************************************************/
/* Structure                                                                                */
/********************************************************************************************/
typedef union {
    struct {
        td_u32 reserved : 4;
        td_u32 period   : 28;
    } bits;
    td_u32 u32;
} _gpio_pwm_cfg_v2;

typedef union {
    struct {
        td_u32 enable   : 1;
        td_u32 inv      : 1;
        td_u32 reserved : 2;
        td_u32 duty     : 28;
    } bits;
    td_u32 u32;
} _gpio_pwm_ctrl_v2;

typedef union {
    struct {
        td_u32 period   : 28;
        td_u32 reserved : 4;
    } bits;
    td_u32 u32;
} _gpio_pwm_state0_v2;

typedef union {
    struct {
        td_u32 duty     : 28;
        td_u32 reserved : 4;
    } bits;
    td_u32 u32;
} _gpio_pwm_state1_v2;

typedef union {
    struct {
        td_u32 reserved : 4;
        td_u32 period   : 28;
    } bits;
    td_u32 u32;
} _led_pwm_cfg_v2;

typedef union {
    struct {
        td_u32 enable   : 1;
        td_u32 inv      : 1;
        td_u32 reserved : 2;
        td_u32 duty     : 28;
    } bits;
    td_u32 u32;
} _led_pwm_ctrl_v2;

typedef union {
    struct {
        td_u32 period   : 28;
        td_u32 reserved : 4;
    } bits;
    td_u32 u32;
} _led_pwm_state0_v2;

typedef union {
    struct {
        td_u32 duty     : 28;
        td_u32 reserved : 4;
    } bits;
    td_u32 u32;
} _led_pwm_state1_v2;

/*
   pwm num      : 4 (下电区)
   led_pwm num  : 1 (常电区)
*/
typedef struct { /* pwm: 4, led_pwm: 1 */
    td_u32 pwm_phy_addr;                    /* 0xF8B30000 */
    td_u32 pwm_addr_space_size;             /* 0x1000 */
    volatile td_void *pwm_base_addr;
    td_u32 pwm_clk_freq;                    /* 54MHz */
    td_u16 pwm_base_addr_offset;            /* 0x20 */
    td_u16 pwm_num;                         /* 4 */
    td_u16 pwm_bit_num;                     /* 8 */

    td_u32 led_pwm_phy_addr;                /* 0xF800A000 */
    td_u32 led_pwm_addr_space_size;         /* 0x1000 */
    volatile td_void *led_pwm_base_addr;
    td_u32 led_pwm_clk_freq;                /* 24MHz */
    td_u16 led_pwm_num;                     /* 1 */

    td_u16 bri_pwm_num;                     /* 4 */

    td_u32 pwm_freq_critical;               /* 10Hz */

    td_u16 offset_cfg;                      /* 0x0 */
    td_u16 offset_ctrl;                     /* 0x4 */
    td_u16 offset_state0_period;            /* 0x8 */
    td_u16 offset_state1_duty;              /* 0xC */
} pwm_info_v2;

/********************************************************************************************/
/* Globals                                                                                  */
/********************************************************************************************/
static pwm_info_v2 g_pwm_info_v2 = {0};

/********************************************************************************************
  Function Implementation
********************************************************************************************/
static td_s32 _pwm_get_gpio_pwm_reg_addr_v2(td_void)
{
    td_s32 ret = TD_SUCCESS;
    pwm_info_v2 *v2 = &g_pwm_info_v2;

    v2->pwm_base_addr = osal_ioremap_nocache(v2->pwm_phy_addr, v2->pwm_addr_space_size);
    pwm_check_param(ret, TD_FAILURE, v2->pwm_base_addr == TD_NULL, goto out);

out:
    return ret;
}

static td_s32 _pwm_get_led_pwm_reg_addr_v2(td_void)
{
    td_s32 ret = TD_SUCCESS;
    pwm_info_v2 *v2 = &g_pwm_info_v2;

    v2->led_pwm_base_addr = osal_ioremap_nocache(v2->led_pwm_phy_addr, v2->led_pwm_addr_space_size);
    pwm_check_param(ret, TD_FAILURE, v2->led_pwm_base_addr == TD_NULL, goto out);

out:
    return ret;
}

static td_s32 _pwm_get_regs_v2(td_u32 pwm_no, pwm_reg_s *reg)
{
    td_s32 ret = TD_SUCCESS;
    const pwm_info_v2 *v2 = &g_pwm_info_v2;

    pwm_check_param(ret, TD_FAILURE, reg == TD_NULL, goto out);

    if (pwm_no < v2->pwm_num) { /* The pwm_no of pwm is 0~3 */
        reg->cfg    = (uintptr_t)(v2->pwm_base_addr + v2->pwm_base_addr_offset * pwm_no + v2->offset_cfg);
        reg->ctrl   = (uintptr_t)(v2->pwm_base_addr + v2->pwm_base_addr_offset * pwm_no + v2->offset_ctrl);
        reg->state0 = (uintptr_t)(v2->pwm_base_addr + v2->pwm_base_addr_offset * pwm_no + v2->offset_state0_period);
        reg->state1 = (uintptr_t)(v2->pwm_base_addr + v2->pwm_base_addr_offset * pwm_no + v2->offset_state1_duty);
    } else if (pwm_no < (v2->pwm_num + v2->led_pwm_num)) { /* The pwm_no of led_pwm is 4 */
        reg->cfg    = (uintptr_t)(v2->led_pwm_base_addr + v2->offset_cfg);
        reg->ctrl   = (uintptr_t)(v2->led_pwm_base_addr + v2->offset_ctrl);
        reg->state0 = (uintptr_t)(v2->led_pwm_base_addr + v2->offset_state0_period);
        reg->state1 = (uintptr_t)(v2->led_pwm_base_addr + v2->offset_state1_duty);
    } else if (pwm_no < (v2->pwm_num + v2->led_pwm_num + v2->bri_pwm_num)) { /* 5,6,7,8 is BRI_PWM0 - BRI_PWM3 */
        soc_log_info("bri pwm is not implemented currently!\n");
        ret = TD_SUCCESS;
        goto out;
    } else {
        soc_log_err("[get_regs] Invalid pwm_no %u for v2! The range is 0~%u\n",
            pwm_no, v2->pwm_num + v2->led_pwm_num + v2->bri_pwm_num - 1);
        ret = TD_FAILURE;
        goto out;
    }

out:
    return ret;
}

static td_s32 _pwm_get_freq_v2(td_u32 pwm_no, td_u32 *freq)
{
    td_s32 ret = TD_SUCCESS;
    pwm_info_v2 *v2 = &g_pwm_info_v2;

    pwm_check_param(ret, TD_FAILURE, freq == TD_NULL, goto out);

    if (pwm_no < v2->pwm_num) { /* The pwm_no of pwm is 0~3 */
        *freq = v2->pwm_clk_freq; /* 54MHz */
    } else if (pwm_no < (v2->pwm_num + v2->led_pwm_num)) { /* The pwm_no of led_pwm is 4 */
        *freq = v2->led_pwm_clk_freq; /* 24MHz */
    } else if (pwm_no < (v2->pwm_num + v2->led_pwm_num + v2->bri_pwm_num)) { /* 5,6,7,8 is BRI_PWM0 - BRI_PWM3 */
        soc_log_info("bri pwm is not implemented currently!\n");
        ret = TD_SUCCESS;
        goto out;
    } else {
        soc_log_err("[get_freq] Invalid pwm_no %u for v2! The range is 0~%u\n",
            pwm_no, v2->pwm_num + v2->led_pwm_num + v2->bri_pwm_num - 1);
        ret = TD_FAILURE;
        goto out;
    }

out:
    return ret;
}

static td_s32 _gpio_pwm_get_state_v2(td_u32 pwm_no, ext_drv_pwm_attr *pwm_attr)
{
    td_s32 ret;
    pwm_reg_s reg = {0};
    td_u32 freq;
    _gpio_pwm_state0_v2 state0;
    _gpio_pwm_state1_v2 state1;
    _gpio_pwm_ctrl_v2 ctrl;

    pwm_check_param(ret, TD_FAILURE, pwm_attr == TD_NULL, goto out);

    pwm_func_call(ret, _pwm_get_freq_v2(pwm_no, &freq), goto out);

    pwm_func_call(ret, _pwm_get_regs_v2(pwm_no, &reg), goto out);

    state0.u32 = (uintptr_t)osal_readl((td_void *)(uintptr_t)reg.state0);
    state1.u32 = (uintptr_t)osal_readl((td_void *)(uintptr_t)reg.state1);
    ctrl.u32   = (uintptr_t)osal_readl((td_void *)(uintptr_t)reg.ctrl);

    pwm_func_call(ret, pwm_get_attr(freq, state0.bits.period, state1.bits.duty, ctrl.bits.inv, pwm_attr), goto out);

out:
    return ret;
}

static td_s32 _led_pwm_get_state_v2(td_u32 pwm_no, ext_drv_pwm_attr *pwm_attr)
{
    td_s32 ret;
    pwm_reg_s reg = {0};
    td_u32 freq;
    _led_pwm_state0_v2 state0;
    _led_pwm_state1_v2 state1;
    _led_pwm_ctrl_v2 ctrl;

    pwm_check_param(ret, TD_FAILURE, pwm_attr == TD_NULL, goto out);

    pwm_func_call(ret, _pwm_get_regs_v2(pwm_no, &reg), goto out);

    pwm_func_call(ret, _pwm_get_freq_v2(pwm_no, &freq), goto out);

    state0.u32 = (uintptr_t)osal_readl((td_void *)(uintptr_t)reg.state0);
    state1.u32 = (uintptr_t)osal_readl((td_void *)(uintptr_t)reg.state1);
    ctrl.u32   = (uintptr_t)osal_readl((td_void *)(uintptr_t)reg.ctrl);

    pwm_func_call(ret, pwm_get_attr(freq, state0.bits.period, state1.bits.duty, ctrl.bits.inv, pwm_attr), goto out);

out:
    return ret;
}

static td_s32 _gpio_pwm_get_attr_v2(td_u32 pwm_no, ext_drv_pwm_attr *pwm_attr)
{
    td_s32 ret;
    pwm_reg_s reg = {0};
    td_u32 freq;
    _gpio_pwm_cfg_v2 cfg;
    _gpio_pwm_ctrl_v2 ctrl;

    pwm_check_param(ret, TD_FAILURE, pwm_attr == TD_NULL, goto out);

    pwm_func_call(ret, _pwm_get_regs_v2(pwm_no, &reg), goto out);

    pwm_func_call(ret, _pwm_get_freq_v2(pwm_no, &freq), goto out);

    cfg.u32  = (uintptr_t)osal_readl((td_void *)(uintptr_t)reg.cfg);
    ctrl.u32 = (uintptr_t)osal_readl((td_void *)(uintptr_t)reg.ctrl);

    pwm_func_call(ret, pwm_get_attr(freq, cfg.bits.period, ctrl.bits.duty, ctrl.bits.inv, pwm_attr), goto out);

out:
    return ret;
}

static td_s32 _led_pwm_get_attr_v2(td_u32 pwm_no, ext_drv_pwm_attr *pwm_attr)
{
    td_s32 ret;
    pwm_reg_s reg = {0};
    td_u32 freq;
    _led_pwm_cfg_v2 cfg;
    _led_pwm_ctrl_v2 ctrl;

    pwm_check_param(ret, TD_FAILURE, pwm_attr == TD_NULL, goto out);

    pwm_func_call(ret, _pwm_get_regs_v2(pwm_no, &reg), goto out);

    pwm_func_call(ret, _pwm_get_freq_v2(pwm_no, &freq), goto out);

    cfg.u32  = (uintptr_t)osal_readl((td_void *)(uintptr_t)reg.cfg);
    ctrl.u32 = (uintptr_t)osal_readl((td_void *)(uintptr_t)reg.ctrl);

    pwm_func_call(ret, pwm_get_attr(freq, cfg.bits.period, ctrl.bits.duty, ctrl.bits.inv, pwm_attr), goto out);

out:
    return ret;
}

static td_s32 _gpio_pwm_set_attr_v2(td_u32 pwm_no, const ext_drv_pwm_attr *pwm_attr)
{
    td_s32 ret;
    const pwm_info_v2 *v2 = &g_pwm_info_v2;
    pwm_reg_s reg = {0};
    pwm_info info = {0};
    _gpio_pwm_cfg_v2 cfg = {
        .bits.period = ~0,
        .u32 = ~0
    };

    pwm_check_param(ret, TD_FAILURE, pwm_attr == TD_NULL, goto out);

    pwm_func_call(ret, _pwm_get_regs_v2(pwm_no, &reg), goto out);

    pwm_func_call(ret, _pwm_get_freq_v2(pwm_no, &info.pwm_clk_freq), goto out);
    info.pwm_freq_critical = v2->pwm_freq_critical;
    info.period_duty_offset = pwm_get_bit_count(cfg.u32) - pwm_get_bit_count(cfg.bits.period);
    info.pwm_reg = &reg;
    info.pwm_attr = pwm_attr;

    pwm_func_call(ret, pwm_set_attr(&info), goto out);

out:
    return ret;
}

static td_s32 _led_pwm_set_attr_v2(td_u32 pwm_no, const ext_drv_pwm_attr *pwm_attr)
{
    td_s32 ret;
    const pwm_info_v2 *v2 = &g_pwm_info_v2;
    pwm_reg_s reg = {0};
    pwm_info info = {0};
    _led_pwm_cfg_v2 cfg = {
        .bits.period = ~0,
        .u32 = ~0
    };

    pwm_check_param(ret, TD_FAILURE, pwm_attr == TD_NULL, goto out);

    pwm_func_call(ret, _pwm_get_regs_v2(pwm_no, &reg), goto out);

    pwm_func_call(ret, _pwm_get_freq_v2(pwm_no, &info.pwm_clk_freq), goto out);
    info.pwm_freq_critical = v2->pwm_freq_critical;
    info.period_duty_offset = pwm_get_bit_count(cfg.u32) - pwm_get_bit_count(cfg.bits.period);
    info.pwm_attr = pwm_attr;
    info.pwm_reg = &reg;

    pwm_func_call(ret, pwm_set_attr(&info), goto out);

out:
    return ret;
}

static td_s32 _gpio_pwm_set_enable_v2(td_u32 pwm_no, td_bool enable)
{
    td_s32 ret;
    pwm_reg_s reg = {0};
    _gpio_pwm_ctrl_v2 ctrl;

    pwm_func_call(ret, _pwm_get_regs_v2(pwm_no, &reg), goto out);

    ctrl.u32 = (uintptr_t)osal_readl((td_void *)(uintptr_t)reg.ctrl);

    ctrl.bits.enable = enable;

    osal_writel(ctrl.u32, (td_void *)(uintptr_t)reg.ctrl);

out:
    return ret;
}

static td_s32 _led_pwm_set_enable_v2(td_u32 pwm_no, td_bool enable)
{
    td_s32 ret;
    pwm_reg_s reg = {0};
    _led_pwm_ctrl_v2 ctrl;

    pwm_func_call(ret, _pwm_get_regs_v2(pwm_no, &reg), goto out);

    ctrl.u32 = (uintptr_t)osal_readl((td_void *)(uintptr_t)reg.ctrl);

    ctrl.bits.enable = enable;

    osal_writel(ctrl.u32, (td_void *)(uintptr_t)reg.ctrl);

out:
    return ret;
}

static td_s32 _gpio_pwm_get_enable_v2(td_u32 pwm_no, td_bool *enable)
{
    td_s32 ret;
    pwm_reg_s reg = {0};
    _gpio_pwm_ctrl_v2 ctrl;

    pwm_check_param(ret, TD_FAILURE, enable == TD_NULL, goto out);

    pwm_func_call(ret, _pwm_get_regs_v2(pwm_no, &reg), goto out);

    ctrl.u32 = (uintptr_t)osal_readl((td_void *)(uintptr_t)reg.ctrl);

    *enable = ctrl.bits.enable;

out:
    return ret;
}

static td_s32 _led_pwm_get_enable_v2(td_u32 pwm_no, td_bool *enable)
{
    td_s32 ret;
    pwm_reg_s reg = {0};
    _led_pwm_ctrl_v2 ctrl;

    pwm_check_param(ret, TD_FAILURE, enable == TD_NULL, goto out);

    pwm_func_call(ret, _pwm_get_regs_v2(pwm_no, &reg), goto out);

    ctrl.u32 = (uintptr_t)osal_readl((td_void *)(uintptr_t)reg.ctrl);

    *enable = ctrl.bits.enable;

out:
    return ret;
}

td_s32 pwm_deinit_v2(td_void)
{
    pwm_info_v2 *v2 = &g_pwm_info_v2;

    if (v2->pwm_base_addr != TD_NULL) {
        osal_iounmap((td_void *)v2->pwm_base_addr, OSAL_IOUNMAP_SIZE);
        v2->pwm_base_addr = TD_NULL;
    }

    if (v2->led_pwm_base_addr != TD_NULL) {
        osal_iounmap((td_void *)v2->led_pwm_base_addr, OSAL_IOUNMAP_SIZE);
        v2->led_pwm_base_addr = TD_NULL;
    }

    return TD_SUCCESS;
}

td_s32 pwm_init_v2(td_void)
{
    td_s32 ret = TD_SUCCESS;
    pwm_info_v2 *v2 = &g_pwm_info_v2;

    v2->pwm_phy_addr                  = 0xF8B30000;   /* pwm physical addr : 0xF8B30000 */
    v2->pwm_addr_space_size           = 0x1000;       /* pwm addr space size : 0x1000 */
    pwm_func_call(ret, _pwm_get_gpio_pwm_reg_addr_v2(), goto deinit);
    v2->pwm_clk_freq                  = 54000000;     /* 54000000 MHz */
    v2->pwm_base_addr_offset          = 0x20;         /* pwm_base_addr_offset : 0x20 */
    v2->pwm_num                       = 4;            /* pwm_num number : 4 */
    v2->pwm_bit_num                   = 8;            /* gpio_pwm_bit_num : 8 */

    v2->led_pwm_phy_addr              = 0xF800A000;   /* led pwm physical addr : 0xF800A000 */
    v2->led_pwm_addr_space_size       = 0x1000;       /* led pwm addr space size : 0x1000 */
    pwm_func_call(ret, _pwm_get_led_pwm_reg_addr_v2(), goto deinit);
    v2->led_pwm_clk_freq              = 24000000;     /* led_pwm_clk_freq : 24000000 MHz */
    v2->led_pwm_num                   = 1;            /* led_pwm_num : 1 */

    v2->bri_pwm_num                   = 4;            /* bri_pwm_num : 4 */

    v2->pwm_freq_critical             = 10;           /* 10 Hz */

    v2->offset_cfg                    = 0x0;          /* offset_cfg : 0x0 */
    v2->offset_ctrl                   = 0x4;          /* offset_ctrl : 0x4 */
    v2->offset_state0_period          = 0x8;          /* offset_state0_period : 0x8 */
    v2->offset_state1_duty            = 0xC;          /* offset_state1_duty : 0xC */

    goto out;

deinit:
    pwm_func_call(ret, pwm_deinit_v2(), goto out);
out:
    return ret;
}

td_s32 pwm_get_state_v2(td_u32 pwm_no, ext_drv_pwm_attr *pwm_attr)
{
    td_s32 ret;
    const pwm_info_v2 *v2 = &g_pwm_info_v2;

    pwm_check_param(ret, TD_FAILURE, pwm_attr == TD_NULL, goto out);

    if (pwm_no < v2->pwm_num) { /* The pwm_no of pwm is 0~3 */
        pwm_func_call(ret, _gpio_pwm_get_state_v2(pwm_no, pwm_attr), goto out);
    } else if (pwm_no < (v2->pwm_num + v2->led_pwm_num)) { /* The pwm_no of led_pwm is 4 */
        pwm_func_call(ret, _led_pwm_get_state_v2(pwm_no, pwm_attr), goto out);
    } else if (pwm_no < (v2->pwm_num + v2->led_pwm_num + v2->bri_pwm_num)) { /* 5,6,7,8 is BRI_PWM0 - BRI_PWM3 */
        soc_log_info("bri pwm is not implemented currently!\n");
        ret = TD_SUCCESS;
        goto out;
    } else {
        soc_log_err("[get_state] Invalid pwm_no %u for v2! The range is 0~%u\n",
            pwm_no, v2->pwm_num + v2->led_pwm_num + v2->bri_pwm_num - 1);
        ret = TD_FAILURE;
        goto out;
    }

out:
    return ret;
}

td_s32 pwm_get_attr_v2(td_u32 pwm_no, ext_drv_pwm_attr *pwm_attr)
{
    td_s32 ret;
    const pwm_info_v2 *v2 = &g_pwm_info_v2;

    pwm_check_param(ret, TD_FAILURE, pwm_attr == TD_NULL, goto out);

    if (pwm_no < v2->pwm_num) { /* The pwm_no of pwm is 0~3 */
        pwm_func_call(ret, _gpio_pwm_get_attr_v2(pwm_no, pwm_attr), goto out);
    } else if (pwm_no < (v2->pwm_num + v2->led_pwm_num)) { /* The pwm_no of led_pwm is 4 */
        pwm_func_call(ret, _led_pwm_get_attr_v2(pwm_no, pwm_attr), goto out);
    } else if (pwm_no < (v2->pwm_num + v2->led_pwm_num + v2->bri_pwm_num)) { /* 5,6,7,8 is BRI_PWM0 - BRI_PWM3 */
        soc_log_info("bri pwm is not implemented currently!\n");
        ret = TD_SUCCESS;
        goto out;
    } else {
        soc_log_err("[get_attr] Invalid pwm_no %u for v2! The range is 0~%u\n",
            pwm_no, v2->pwm_num + v2->led_pwm_num + v2->bri_pwm_num - 1);
        ret = TD_FAILURE;
        goto out;
    }

out:
    return ret;
}

td_s32 pwm_set_attr_v2(td_u32 pwm_no, const ext_drv_pwm_attr *pwm_attr)
{
    td_s32 ret;
    const pwm_info_v2 *v2 = &g_pwm_info_v2;

    pwm_check_param(ret, TD_FAILURE, pwm_attr == TD_NULL, goto out);

    if (pwm_no < v2->pwm_num) { /* The pwm_no of pwm is 0~3 */
        pwm_func_call(ret, _gpio_pwm_set_attr_v2(pwm_no, pwm_attr), goto out);
    } else if (pwm_no < (v2->pwm_num + v2->led_pwm_num)) { /* The pwm_no of led_pwm is 4 */
        pwm_func_call(ret, _led_pwm_set_attr_v2(pwm_no, pwm_attr), goto out);
    } else if (pwm_no < (v2->pwm_num + v2->led_pwm_num + v2->bri_pwm_num)) { /* 5,6,7,8 is BRI_PWM0 - BRI_PWM3 */
        soc_log_info("bri pwm is not implemented currently!\n");
        ret = TD_SUCCESS;
        goto out;
    } else {
        soc_log_err("[set_attr] Invalid pwm_no %u for v2! The range is 0~%u\n",
            pwm_no, v2->pwm_num + v2->led_pwm_num + v2->bri_pwm_num - 1);
        ret = TD_FAILURE;
        goto out;
    }

out:
    return ret;
}

td_s32 pwm_set_enable_v2(td_u32 pwm_no, td_bool enable)
{
    td_s32 ret;
    const pwm_info_v2 *v2 = &g_pwm_info_v2;

    if (pwm_no < v2->pwm_num) { /* The pwm_no of pwm is 0~3 */
        pwm_func_call(ret, _gpio_pwm_set_enable_v2(pwm_no, enable), goto out);
    } else if (pwm_no < (v2->pwm_num + v2->led_pwm_num)) { /* The pwm_no of led_pwm is 4 */
        pwm_func_call(ret, _led_pwm_set_enable_v2(pwm_no, enable), goto out);
    } else if (pwm_no < (v2->pwm_num + v2->led_pwm_num + v2->bri_pwm_num)) { /* 5,6,7,8 is BRI_PWM0 - BRI_PWM3 */
        soc_log_info("bri pwm is not implemented currently!\n");
        ret = TD_SUCCESS;
        goto out;
    } else {
        soc_log_err("[set_enable] Invalid pwm_no %u for v2! The range is 0~%u\n",
            pwm_no, v2->pwm_num + v2->led_pwm_num + v2->bri_pwm_num - 1);
        ret = TD_FAILURE;
        goto out;
    }

out:
    return ret;
}

td_s32 pwm_get_enable_v2(td_u32 pwm_no, td_bool *enable)
{
    td_s32 ret;
    const pwm_info_v2 *v2 = &g_pwm_info_v2;

    pwm_check_param(ret, TD_FAILURE, enable == TD_NULL, goto out);

    if (pwm_no < v2->pwm_num) { /* The pwm_no of pwm is 0~3 */
        pwm_func_call(ret, _gpio_pwm_get_enable_v2(pwm_no, enable), goto out);
    } else if (pwm_no < (v2->pwm_num + v2->led_pwm_num)) { /* The pwm_no of led_pwm is 4 */
        pwm_func_call(ret, _led_pwm_get_enable_v2(pwm_no, enable), goto out);
    } else if (pwm_no < (v2->pwm_num + v2->led_pwm_num + v2->bri_pwm_num)) { /* 5,6,7,8 is BRI_PWM0 - BRI_PWM3 */
        soc_log_info("bri pwm is not implemented currently!\n");
        ret = TD_SUCCESS;
        goto out;
    } else {
        soc_log_err("[get_enable] Invalid pwm_no %u for v2! The range is 0~%u\n",
            pwm_no, v2->pwm_num + v2->led_pwm_num + v2->bri_pwm_num - 1);
        ret = TD_FAILURE;
        goto out;
    }

out:
    return ret;
}

td_s32 pwm_send_signal_v2(td_u32 pwm_no, td_u32 carrier_signal_duration_us, td_u32 low_level_signal_duration_us)
{
    soc_log_info("RESERVED5 chip not support pwm_send_signal!\n");

    return TD_SUCCESS;
}