/*
 * Copyright (c) Hisilicon Technologies Co., Ltd. 2012-2019. All rights reserved.
 * Description: decoder
 * Author: Hisilicon
 * Create: 2012-04-22
 */

#ifndef _DMCU_HAL_H_
#define _DMCU_HAL_H_

#include "td_type.h"
#include "soc_osal.h"
#include "drv_dmcu_sys.h"

#define IOMMU_SEC_IRQ_NUM (26 + 4)
#define IOMMU_NO_SEC_IRQ_NUM (26 + 5)

#define MEM_PT_SIZE_MAX 0x400000
#define MEM_MAX_ADDR 0xffffffff

#if (defined(LOSCFG_FAMILY_RESERVED19) || defined(LOSCFG_FAMILY_HI3751V811))
#define SMMU_SCR 0x0
#define COMMON_CTRL 0x4
#define INT_MASK_SEC 0x10
#define INT_CLR_SEC 0x1C
#define INT_MASK_NO_SEC 0x20
#define INT_CLR_NO_SEC 0x2C
#define SCB_TTBR 0x2E4
#define SCB_TTBR_H 0x2E0
#define CB_TTBR 0x2EC
#define CB_TTBR_H 0x2E8
#define ERR_S_RD_ADDR 0x2F0
#define ERR_S_RD_ADDR_H 0x2F4
#define ERR_S_WR_ADDR 0x2FC
#define ERR_S_WR_ADDR_H 0x2F8
#define ERR_NS_RD_ADDR 0x304
#define ERR_NS_RD_ADDR_H 0x300
#define ERR_NS_WR_ADDR 0x30C
#define ERR_NS_WR_ADDR_H 0x308

#define CMD_BUF_STATE 0x20
#define TLB_FLUSH 0x58
#define IOMMU_MAP_SIZE 0x1000
#define DMCU_MAX_PT_SIZE (4 * 1024 * 1024)
#else
#define SMMU_SCR 0x0
#define COMMON_CTRL 0x4
#define CLK_GT_EN 0x8
#define INT_MASK_SEC 0x10
#define INT_CLR_SEC 0x1C
#define INT_MASK_NO_SEC 0x20
#define INT_CLR_NO_SEC 0x2C
#define SCB_TTBR 0x100
#define SCB_TTBR_H 0x104
#define CB_TTBR 0x200
#define CB_TTBR_H 0x204
#define SCMD_TAG_RD_EN 0x110
#define SCMD_TAG_WR_EN 0x120
#define ERR_S_RD_ADDR 0x130
#define ERR_S_RD_ADDR_H 0x134
#define ERR_S_WR_ADDR 0x138
#define ERR_S_WR_ADDR_H 0x13c
#define CMD_TAG_RD_EN 0x210
#define CMD_TAG_WR_EN 0x220
#define ERR_NS_RD_ADDR 0x230
#define ERR_NS_RD_ADDR_H 0x234
#define ERR_NS_WR_ADDR 0x238
#define ERR_NS_WR_ADDR_H 0x23c

#define CMD_BUF_STATE 0x20
#define COMMON_TCU 0x10
#define TLB_FLUSH 0x58
#define IOMMU_MAP_SIZE 0x1000
#define DMCU_MAX_PT_SIZE (4 * 1024 * 1024)
#endif

#define DCMAINT 0x7C3

#define write_custom_csr(reg_addr, val)                            \
    do {                                                           \
        if (__builtin_constant_p(val) && (unsigned int)(val) < 32) \
            __asm__ __volatile__("li t0, "                         \
                "%0" ::"i"(val));                                  \
        else                                                       \
            __asm__ __volatile__("mv t0, "                         \
                "%0" ::"r"(val));                                  \
        __asm__ __volatile__("csrw %0, t0" ::"i"(reg_addr));       \
    } while (0)


typedef enum {
    DMCU_IOMMU_ERR_ADDR_RD_SEC = 0,
    DMCU_IOMMU_ERR_ADDR_WR_SEC = 1,
    DMCU_IOMMU_ERR_ADDR_RD_NON_SEC = 2,
    DMCU_IOMMU_ERR_ADDR_WR_NON_SEC = 3,
    DMCU_IOMMU_ERR_ADDR_MAX,
} iommu_err_addr_index;

#define DMCU_IOMMU_REG_INFO_SIZE 0x400
#define DMCU_IOMMU_ERR_ADDR_SIZE 256

#define wr_iommu_reg_(data, reg)            \
    do {                                    \
        *(volatile td_u32 *)(reg) = (data); \
    } while (0)

#define rd_iommu_reg_(data, reg)            \
    do {                                    \
        (data) = *(volatile td_u32 *)(reg); \
    } while (0)

#define WR_IOMMU_REG wr_iommu_reg_
#define RD_IOMMU_REG rd_iommu_reg_

typedef struct {
    td_u32 pt_sec_addr;
    td_u32 pt_sec_err_rd_addr;
    td_u32 pt_sec_err_wt_addr;
    td_u32 pt_no_sec_addr;
    td_u32 pt_no_sec_err_rd_addr;
    td_u32 pt_no_sec_err_wt_addr;
} dmcu_iommu_pt_addr;

typedef struct {
    osal_spinlock spin_lock;
    td_u8 *comm_base_reg;
    td_u8 *master_base_reg;
    dmcu_iommu_pt_addr pt_addr;
} iommu_ctx;

td_s32 dmcu_iommu_init(const dmcu_iommu_pt_addr *pt_addr);
td_s32 dmcu_iommu_deinit(td_void);
td_s32 dmcu_iommu_flush_tlb(td_bool flush_cache);
void dmcu_flush_d_cache_by_all(void);
td_void dmcu_hal_set_uart_pinmux(td_void);
#endif