// Copyright 2015, VIXL authors // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: // // * Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. // * Redistributions in binary form must reproduce the above copyright notice, // this list of conditions and the following disclaimer in the documentation // and/or other materials provided with the distribution. // * Neither the name of ARM Limited nor the names of its contributors may be // used to endorse or promote products derived from this software without // specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // --------------------------------------------------------------------- // This file is auto generated using tools/generate_simulator_traces.py. // // PLEASE DO NOT EDIT. // --------------------------------------------------------------------- #ifndef VIXL_SIM_FCVTAS_XH_TRACE_AARCH64_H_ #define VIXL_SIM_FCVTAS_XH_TRACE_AARCH64_H_ const int64_t kExpected_fcvtas_xh[] = { INT64_C(0), INT64_C(0), INT64_C(0), INT64_C(1), INT64_C(1), INT64_C(1), INT64_C(1), INT64_C(1), INT64_C(2), INT64_C(10), INT64_C(65504), INT64_C(9223372036854775807), INT64_C(0), INT64_C(0), INT64_C(0), INT64_C(0), INT64_C(0), INT64_C(0), INT64_C(0), INT64_C(0), INT64_C(0), INT64_C(0), -INT64_C(1), -INT64_C(1), -INT64_C(1), -INT64_C(1), -INT64_C(1), -INT64_C(2), -INT64_C(10), -INT64_C(65504), -INT64_C(9223372036854775807) - 1, INT64_C(0), INT64_C(0), INT64_C(0), INT64_C(0), INT64_C(0), INT64_C(0), INT64_C(0), INT64_C(1024), INT64_C(1025), INT64_C(1026), INT64_C(1027), INT64_C(1347), INT64_C(2044), INT64_C(2045), INT64_C(2046), INT64_C(2047), INT64_C(512), INT64_C(513), INT64_C(513), INT64_C(514), INT64_C(913), INT64_C(1022), INT64_C(1023), INT64_C(1023), INT64_C(1024), INT64_C(256), INT64_C(256), INT64_C(257), INT64_C(257), INT64_C(333), INT64_C(511), INT64_C(511), INT64_C(512), INT64_C(512), -INT64_C(1024), -INT64_C(1025), -INT64_C(1026), -INT64_C(1027), -INT64_C(1347), -INT64_C(2044), -INT64_C(2045), -INT64_C(2046), -INT64_C(2047), -INT64_C(512), -INT64_C(513), -INT64_C(513), -INT64_C(514), -INT64_C(913), -INT64_C(1022), -INT64_C(1023), -INT64_C(1023), -INT64_C(1024), -INT64_C(256), -INT64_C(256), -INT64_C(257), -INT64_C(257), -INT64_C(333), -INT64_C(511), -INT64_C(511), -INT64_C(512), -INT64_C(512), INT64_C(0), INT64_C(0), INT64_C(0), INT64_C(0), INT64_C(0), INT64_C(0), INT64_C(0), INT64_C(0), INT64_C(0), }; const unsigned kExpectedCount_fcvtas_xh = 101; #endif // VIXL_SIM_FCVTAS_XH_TRACE_AARCH64_H_