/* * Copyright (c) Hisilicon Technologies Co., Ltd. 2019-2021. All rights reserved. * Description: tsr2rcipher hal func impl. * Author: Hisilicon * Create: 2019-08-02 */ #include "hal_tsr2rcipher.h" #include "td_type.h" #include "osal_ext.h" #include "soc_log.h" #include "drv_sys_ext.h" #include "drv_tsr2rcipher_define.h" #include "drv_tsr2rcipher_func.h" #include "drv_tsr2rcipher_reg.h" /* Tsr2rcipher Rx Config */ td_void tsc_hal_rx_config(const struct tsr2rcipher_mgmt *mgmt, td_u32 id, enum tsc_buf_type buf_type) { if (mgmt == TD_NULL) { soc_log_err("mgmt is null!\n"); return; } tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt); /* enable rx interrupt */ tsc_hal_rx_set_int(mgmt, id, TD_TRUE, TD_FALSE); /* rx ctrl */ tsc_hal_rx_set_ctrl(mgmt, id, buf_type, 0); } /* Tsr2rcipher Rx DeConfig */ td_void tsc_hal_rx_de_config(const struct tsr2rcipher_mgmt *mgmt, td_u32 id) { if (mgmt == TD_NULL) { soc_log_err("mgmt is null!\n"); return; } tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt); /* disable rx interrupt */ tsc_hal_rx_set_int(mgmt, id, TD_FALSE, TD_FALSE); } /* Tsr2rcipher Rx Set Buf */ td_void tsc_hal_rx_set_buf(const struct tsr2rcipher_mgmt *mgmt, td_u32 id, td_u64 src_buf_addr, td_u32 src_buf_len) { if (mgmt == TD_NULL) { soc_log_err("mgmt is null!\n"); return; } tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt); /* rx buffer address */ tsc_hal_rx_set_buf_addr(mgmt, id, src_buf_addr); /* rx buffer len */ tsc_hal_rx_set_buf_len(mgmt, id, src_buf_len); } /* Get DspTor status, OSAL_TURE: description queue not full, can configure new description */ td_bool tsc_hal_rx_get_dsp_tor_status(const struct tsr2rcipher_mgmt *mgmt, td_u32 id) { U_RX_DSPTOR_CTRL reg; if (mgmt == TD_NULL) { soc_log_err("mgmt is null!\n"); return TD_FALSE; } tsr2rcipher_check_condition_return_value(id >= mgmt->ch_cnt, TD_FALSE); reg.u32 = tsc_read_reg_rx(mgmt->io_base, rx_dsptor_ctrl(id)); return (reg.bits.rx_dsptor_full == 0x0); } /* Set the buffer start address, OSAL_TURE: description queue not full, can configure new description */ td_void tsc_hal_rx_set_buf_addr(const struct tsr2rcipher_mgmt *mgmt, td_u32 id, td_u64 src_addr) { U_RX_DSPTOR_START_ADDR reg_addr; U_TSC_RX_CTRL reg_ctrl; if (mgmt == TD_NULL) { soc_log_err("mgmt is null!\n"); return; } tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt); reg_addr.u32 = tsc_read_reg_rx(mgmt->io_base, rx_dsptor_start_addr(id)); reg_ctrl.u32 = tsc_read_reg_rx(mgmt->io_base, tsc_rx_ctrl(id)); /* risk here */ reg_addr.bits.rx_dsptor_start_addr = src_addr & 0x00000000FFFFFFFF; /* 4K align, and 16 bytes align next version */ reg_ctrl.bits.rx_session_id = (src_addr & 0x0000000F00000000) >> 32; /* right shift 32 bits to get high 4 bits */ tsc_write_reg_rx(mgmt->io_base, rx_dsptor_start_addr(id), reg_addr.u32); tsc_write_reg_rx(mgmt->io_base, tsc_rx_ctrl(id), reg_ctrl.u32); } /* Set the buffer Len */ td_void tsc_hal_rx_set_buf_len(const struct tsr2rcipher_mgmt *mgmt, td_u32 id, td_u32 src_len) { U_RX_DSPTOR_LENGTH reg; if (mgmt == TD_NULL) { soc_log_err("mgmt is null!\n"); return; } tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt); reg.u32 = tsc_read_reg_rx(mgmt->io_base, rx_dsptor_length(id)); reg.bits.rx_dsptor_length = src_len / TSR2RCIPHER_TS_PACKAGE_LEN; /* ts package number */ reg.bits.rx_dsptor_cfg = 1; tsc_write_reg_rx(mgmt->io_base, rx_dsptor_length(id), reg.u32); } /* Add the Rx Dsc */ td_void tsc_hal_rx_add_dsc(const struct tsr2rcipher_mgmt *mgmt, td_u32 id) { U_RX_DSPTOR_LENGTH reg; if (mgmt == TD_NULL) { soc_log_err("mgmt is null!\n"); return; } tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt); reg.u32 = tsc_read_reg_rx(mgmt->io_base, rx_dsptor_length(id)); reg.bits.rx_dsptor_cfg = 1; tsc_write_reg_rx(mgmt->io_base, rx_dsptor_length(id), reg.u32); tsc_com_equal(reg.u32, tsc_read_reg_rx(mgmt->io_base, rx_dsptor_length(id))); } /* Set Rx Ctrl */ td_void tsc_hal_rx_set_ctrl(const struct tsr2rcipher_mgmt *mgmt, td_u32 id, enum tsc_buf_type buf_type, td_u32 rx_pkg_th) { U_TSC_RX_CTRL reg; if (mgmt == TD_NULL) { soc_log_err("mgmt is null!\n"); return; } tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt); reg.u32 = tsc_read_reg_rx(mgmt->io_base, tsc_rx_ctrl(id)); reg.bits.rx_buf_type = buf_type; reg.bits.rx_pkt_int_level = rx_pkg_th; tsc_write_reg_rx(mgmt->io_base, tsc_rx_ctrl(id), reg.u32); tsc_com_equal(reg.u32, tsc_read_reg_rx(mgmt->io_base, tsc_rx_ctrl(id))); } /* Set Rx Ctrl */ td_void tsc_hal_rx_set_int(const struct tsr2rcipher_mgmt *mgmt, td_u32 id, td_bool dsc_rd, td_bool rx_pkt) { U_IENA_RX reg; if (mgmt == TD_NULL) { soc_log_err("mgmt is null!\n"); return; } tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt); reg.u32 = tsc_read_reg_rx(mgmt->io_base, iena_rx(id)); reg.bits.iena_rx_dsptor_done = (TD_TRUE == dsc_rd ? 1 : 0); reg.bits.iena_rx_pkt_cnt = (TD_TRUE == rx_pkt ? 1 : 0); tsc_write_reg_rx(mgmt->io_base, iena_rx(id), reg.u32); tsc_com_equal(reg.u32, tsc_read_reg_rx(mgmt->io_base, iena_rx(id))); } /* Get Rx Dsc Rd Total Int status */ td_u32 tsc_hal_rx_get_dsc_rd_total_int_status(const struct tsr2rcipher_mgmt *mgmt) { U_RX_INT_TYPE reg; if (mgmt == TD_NULL) { soc_log_err("mgmt is null!\n"); return 0; } reg.u32 = tsc_read_reg_rx(mgmt->io_base, RX_INT_TYPE); return reg.bits.rx_dsptor_done_int; } /* Get Rx Pkt cnt Total Int status */ td_u32 tsc_hal_rx_get_pkt_cnt_total_int_status(const struct tsr2rcipher_mgmt *mgmt) { U_RX_INT_TYPE reg; if (mgmt == TD_NULL) { soc_log_err("mgmt is null!\n"); return 0; } reg.u32 = tsc_read_reg_rx(mgmt->io_base, RX_INT_TYPE); return reg.bits.rx_pkt_cnt_int; } /* Get the Dsc Rd interrupt status */ td_u32 tsc_hal_rx_get_dsc_rd_int_status(const struct tsr2rcipher_mgmt *mgmt, td_u32 id) { td_u32 reg_index; td_u32 bit_offset; td_u32 reg; if (mgmt == TD_NULL) { soc_log_err("mgmt is null!\n"); return 0; } tsr2rcipher_check_condition_return_value(id >= mgmt->ch_cnt, 0); reg_index = id / INT_FLAG_REG_NUM; bit_offset = id % INT_FLAG_REG_NUM; reg = tsc_read_reg_rx(mgmt->io_base, ista_rx_dsptor0(reg_index)); return (reg & (1U << bit_offset)); } /* Cls Rx Dsc Rd Int status */ td_void tsc_hal_rx_cls_dsc_rd_int_status(const struct tsr2rcipher_mgmt *mgmt, td_u32 id) { U_IRAW_RX reg; U_IRAW_RX reg_cls; if (mgmt == TD_NULL) { soc_log_err("mgmt is null!\n"); return; } tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt); reg.u32 = 0; reg_cls.u32 = 0; reg.bits.iraw_rx_dsptor_done = 1; tsc_write_reg_rx(mgmt->io_base, iraw_rx(id), reg.u32); } /* Get the Rx Pkt cnt interrupt status */ td_u32 tsc_hal_rx_get_pkt_cnt_int_status(const struct tsr2rcipher_mgmt *mgmt, td_u32 id) { td_u32 reg_index; td_u32 bit_offset; td_u32 reg; if (mgmt == TD_NULL) { soc_log_err("mgmt is null!\n"); return 0; } tsr2rcipher_check_condition_return_value(id >= mgmt->ch_cnt, 0); reg_index = id / INT_FLAG_REG_NUM; bit_offset = id % INT_FLAG_REG_NUM; reg = tsc_read_reg_rx(mgmt->io_base, ista_rx_pkt_cnt0(reg_index)); return (reg & (1U << bit_offset)); } /* Cls Rx Pkt cnt Int status */ td_void tsc_hal_rx_cls_pkt_cnt_int_status(const struct tsr2rcipher_mgmt *mgmt, td_u32 id) { U_IRAW_RX reg; U_IRAW_RX reg_cls; if (mgmt == TD_NULL) { soc_log_err("mgmt is null!\n"); return; } tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt); reg.u32 = 0; reg_cls.u32 = 0; reg.bits.iraw_rx_pkt_cnt = 1; tsc_write_reg_rx(mgmt->io_base, iraw_rx(id), reg.u32); } /* Get the Rx Total Dsc Rd interrupt Register value */ td_void tsc_hal_rx_get_dsc_rd_total_int_value(const struct tsr2rcipher_mgmt *mgmt, td_u32 *value_array) { td_u32 i; td_u32 array_cnt; if ((mgmt == TD_NULL) || (value_array == TD_NULL)) { soc_log_err("para is null!\n"); return; } if ((td_s32)mgmt->ch_cnt <= 1) { return; } array_cnt = (mgmt->ch_cnt - 1) / INT_FLAG_REG_NUM; for (i = 0; i < array_cnt; i++) { value_array[i] = tsc_read_reg_rx(mgmt->io_base, ista_rx_dsptor0(i)); } } /* Get the Total Pkt cnt interrupt regitster value */ td_void tsc_hal_rx_get_pkt_cnt_total_int_value(const struct tsr2rcipher_mgmt *mgmt, td_u32 *value_array) { td_u32 i; td_u32 array_cnt; if ((mgmt == TD_NULL) || (value_array == TD_NULL)) { soc_log_err("para is null!\n"); return; } if ((td_s32)mgmt->ch_cnt <= 1) { return; } array_cnt = (mgmt->ch_cnt - 1) / INT_FLAG_REG_NUM; for (i = 0; i < array_cnt; i++) { value_array[i] = tsc_read_reg_rx(mgmt->io_base, ista_rx_pkt_cnt0(i)); } } /* Set Rx Mode Ctrl */ td_void tsc_hal_set_mode_ctl(const struct tsr2rcipher_mgmt *mgmt, struct tsr2rcipher_r_ch *rch, enum tsc_crypt_type crypt_type) { U_TSC_MODE_CTRL reg; if ((mgmt == TD_NULL) || (rch == TD_NULL)) { soc_log_err("para is null!\n"); return; } tsr2rcipher_check_condition_return_void(rch->base.id >= mgmt->ch_cnt); reg.u32 = tsc_read_reg_rx(mgmt->io_base, tsc_mode_ctrl(rch->base.id)); reg.bits.key_id = (rch->ks_handle & 0x000000ff); reg.bits.dsc_type = crypt_type; reg.bits.core_sel = rch->core_type; reg.bits.pl_raw_sel = rch->mode; if (rch->is_odd_key == TD_TRUE) { reg.bits.odd_even_sel = 1; } else { reg.bits.odd_even_sel = 0; } if (rch->is_crc_check == TD_TRUE) { reg.bits.tsc_crc_en = 1; } else { reg.bits.tsc_crc_en = 0; } tsc_write_reg_rx(mgmt->io_base, tsc_mode_ctrl(rch->base.id), reg.u32); reg.bits.tsc_rx_sec_attr = 1; reg.bits.tsc_tx_sec_attr = 1; tsc_com_equal(reg.u32, tsc_read_reg_rx(mgmt->io_base, tsc_mode_ctrl(rch->base.id))); } /* Set Rx Mode Ctrl */ td_void tsc_hal_en_mode_ctl(const struct tsr2rcipher_mgmt *mgmt, td_u32 id) { U_TSC_MODE_CTRL reg; if (mgmt == TD_NULL) { soc_log_err("para is null!\n"); return; } tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt); reg.u32 = tsc_read_reg_rx(mgmt->io_base, tsc_mode_ctrl(id)); reg.bits.tsc_chn_en = 1; tsc_write_reg_rx(mgmt->io_base, tsc_mode_ctrl(id), reg.u32); tsc_com_equal(reg.u32, tsc_read_reg_rx(mgmt->io_base, tsc_mode_ctrl(id))); } /* Set Rx Mode Ctrl */ td_void tsc_hal_dis_mode_ctl(const struct tsr2rcipher_mgmt *mgmt, td_u32 id) { U_TSC_MODE_CTRL reg; if (mgmt == TD_NULL) { soc_log_err("para is null!\n"); return; } tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt); reg.u32 = tsc_read_reg_rx(mgmt->io_base, tsc_mode_ctrl(id)); reg.bits.tsc_chn_en = 0; tsc_write_reg_rx(mgmt->io_base, tsc_mode_ctrl(id), reg.u32); } td_void tsc_hal_clr_chan(const struct tsr2rcipher_mgmt *mgmt, td_u32 id) { td_u32 i = 0; u_tsc_clear_req reg; if (mgmt == TD_NULL) { soc_log_err("para is null!\n"); return; } tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt); reg.u32 = tsc_read_reg_rx(mgmt->io_base, TSC_CLEAR_REQ); reg.bits.tsc_clear_chn_id = id; reg.bits.tsc_clear_chn_req = 1; tsc_write_reg_rx(mgmt->io_base, TSC_CLEAR_REQ, reg.u32); reg.u32 = tsc_read_reg_rx(mgmt->io_base, TSC_CLEAR_REQ); while (reg.bits.tsc_clear_chn_req != 0 && (i++ <= TSC_CHAN_CLEAR_TIMEOUT_CNT)) { osal_msleep(1); reg.u32 = tsc_read_reg_rx(mgmt->io_base, TSC_CLEAR_REQ); } if (i >= TSC_CHAN_CLEAR_TIMEOUT_CNT) { soc_log_err("clear chan time out!\n"); } } td_void tsc_hal_lock_config(const struct tsr2rcipher_mgmt *mgmt, td_u32 id, td_bool is_tee_lock) { u_rx_sec_attr reg; if (mgmt == TD_NULL) { soc_log_err("para is null!\n"); return; } tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt); reg.u32 = tsc_read_reg_rx(mgmt->io_base, rx_sec_attr(id)); if (is_tee_lock == TD_TRUE) { reg.bits.tsc_chn_tee_lock = 1; } else { reg.bits.tsc_chn_ree_lock = 1; } tsc_write_reg_rx(mgmt->io_base, rx_sec_attr(id), reg.u32); } td_void tsc_hal_lock_deconfig(const struct tsr2rcipher_mgmt *mgmt, td_u32 id) { u_rx_sec_attr reg; if (mgmt == TD_NULL) { soc_log_err("para is null!\n"); return; } tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt); reg.u32 = tsc_read_reg_rx(mgmt->io_base, rx_sec_attr(id)); reg.bits.tsc_chn_tee_lock = 0; reg.bits.tsc_chn_ree_lock = 0; tsc_write_reg_rx(mgmt->io_base, rx_sec_attr(id), reg.u32); } /* Tsr2rcipher Tx Config */ td_void tsc_hal_tx_config(const struct tsr2rcipher_mgmt *mgmt, td_u32 id, enum tsc_buf_type buf_type) { if (mgmt == TD_NULL) { soc_log_err("para is null!\n"); return; } tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt); /* enable tx interrupt */ tsc_hal_tx_set_int(mgmt, id, TD_TRUE, TD_FALSE); /* tx ctrl */ tsc_hal_tx_set_ctrl(mgmt, id, buf_type, 0); } /* Tsr2rcipher Tx DeConfig */ td_void tsc_hal_tx_de_config(const struct tsr2rcipher_mgmt *mgmt, td_u32 id) { if (mgmt == TD_NULL) { soc_log_err("para is null!\n"); return; } tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt); /* disable rx interrupt */ tsc_hal_tx_set_int(mgmt, id, TD_FALSE, TD_FALSE); } /* Tsr2rcipher Tx Set Buffer */ td_void tsc_hal_tx_set_buf(const struct tsr2rcipher_mgmt *mgmt, td_u32 id, td_u64 dst_buf_addr, td_u32 dst_buf_len) { if (mgmt == TD_NULL) { soc_log_err("para is null!\n"); return; } tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt); /* tx buffer address */ tsc_hal_tx_set_buf_addr(mgmt, id, dst_buf_addr); /* tx buffer len */ tsc_hal_tx_set_buf_len(mgmt, id, dst_buf_len); } /* Get DspTor status, OSAL_TURE: description queue not full, can configure new description */ td_bool tsc_hal_tx_get_dsp_tor_status(const struct tsr2rcipher_mgmt *mgmt, td_u32 id) { U_TX_DSPTOR_CTRL reg; if (mgmt == TD_NULL) { soc_log_err("para is null!\n"); return TD_FALSE; } tsr2rcipher_check_condition_return_value(id >= mgmt->ch_cnt, TD_FALSE); reg.u32 = tsc_read_reg_tx(mgmt->io_base, tx_dsptor_ctrl(id)); return (reg.bits.tx_dsptor_full == 0x0); } /* Set the buffer start address */ td_void tsc_hal_tx_set_buf_addr(const struct tsr2rcipher_mgmt *mgmt, td_u32 id, td_u64 dst_addr) { U_TX_DSPTOR_START_ADDR reg_addr; U_TSC_TX_CTRL reg_ctrl; if (mgmt == TD_NULL) { soc_log_err("para is null!\n"); return; } tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt); reg_addr.u32 = tsc_read_reg_tx(mgmt->io_base, tx_dsptor_start_addr(id)); reg_ctrl.u32 = tsc_read_reg_tx(mgmt->io_base, TSC_TX_CTRL(id)); /* risk here */ reg_addr.bits.tx_dsptor_start_addr = dst_addr & 0x00000000FFFFFFFF; /* 4K align, and 16 bytes align next version */ reg_ctrl.bits.tx_session_id = (dst_addr & 0x0000000F00000000) >> 32; /* right shift 32 bits to get high 4 bits */ tsc_write_reg_tx(mgmt->io_base, tx_dsptor_start_addr(id), reg_addr.u32); tsc_write_reg_tx(mgmt->io_base, TSC_TX_CTRL(id), reg_ctrl.u32); } /* Set the buffer Len */ td_void tsc_hal_tx_set_buf_len(const struct tsr2rcipher_mgmt *mgmt, td_u32 id, td_u32 dst_len) { U_TX_DSPTOR_LENGTH reg; if (mgmt == TD_NULL) { soc_log_err("para is null!\n"); return; } tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt); reg.u32 = tsc_read_reg_tx(mgmt->io_base, tx_dsptor_length(id)); reg.bits.tx_dsptor_length = dst_len / TSR2RCIPHER_TS_PACKAGE_LEN; /* ts package number */ reg.bits.tx_dsptor_cfg = 1; tsc_write_reg_tx(mgmt->io_base, tx_dsptor_length(id), reg.u32); } /* Add the Rx Dsc */ td_void tsc_hal_tx_add_dsc(const struct tsr2rcipher_mgmt *mgmt, td_u32 id) { U_TX_DSPTOR_LENGTH reg; if (mgmt == TD_NULL) { soc_log_err("para is null!\n"); return; } tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt); reg.u32 = tsc_read_reg_tx(mgmt->io_base, tx_dsptor_length(id)); reg.bits.tx_dsptor_cfg = 1; tsc_write_reg_rx(mgmt->io_base, tx_dsptor_length(id), reg.u32); tsc_com_equal(reg.u32, tsc_read_reg_tx(mgmt->io_base, tx_dsptor_length(id))); } /* Set Tx Ctrl */ td_void tsc_hal_tx_set_ctrl(const struct tsr2rcipher_mgmt *mgmt, td_u32 id, enum tsc_buf_type buf_type, td_u32 tx_pkg_th) { U_TSC_TX_CTRL reg; if (mgmt == TD_NULL) { soc_log_err("para is null!\n"); return; } tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt); reg.u32 = tsc_read_reg_tx(mgmt->io_base, TSC_TX_CTRL(id)); reg.bits.tx_buf_type = buf_type; reg.bits.tx_pkt_int_level = tx_pkg_th; reg.bits.tx_press_dis = 0x1; /* disable press */ tsc_write_reg_tx(mgmt->io_base, TSC_TX_CTRL(id), reg.u32); tsc_com_equal(reg.u32, tsc_read_reg_tx(mgmt->io_base, TSC_TX_CTRL(id))); } /* Set Tx interrupt */ td_void tsc_hal_tx_set_int(const struct tsr2rcipher_mgmt *mgmt, td_u32 id, td_bool dsc_rd, td_bool tx_pkt) { U_IENA_TX reg; if (mgmt == TD_NULL) { soc_log_err("para is null!\n"); return; } tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt); reg.u32 = tsc_read_reg_tx(mgmt->io_base, IENA_TX(id)); reg.bits.iena_tx_dsptor_done = (dsc_rd == TD_TRUE ? 1 : 0); reg.bits.iena_tx_pkt_cnt = (tx_pkt == TD_TRUE ? 1 : 0); tsc_write_reg_tx(mgmt->io_base, IENA_TX(id), reg.u32); tsc_com_equal(reg.u32, tsc_read_reg_tx(mgmt->io_base, IENA_TX(id))); } /* Get Tx Dsc Rd Total Int status */ td_u32 tsc_hal_tx_get_dsc_rd_total_int_status(const struct tsr2rcipher_mgmt *mgmt) { U_TX_INT_TYPE reg; if (mgmt == TD_NULL) { soc_log_err("para is null!\n"); return 0; } reg.u32 = tsc_read_reg_tx(mgmt->io_base, TX_INT_TYPE); return reg.bits.tx_dsptor_done_int; } /* Get Tx Pkt cnt Total Int status */ td_u32 tsc_hal_tx_get_pkt_cnt_total_int_status(const struct tsr2rcipher_mgmt *mgmt) { U_TX_INT_TYPE reg; if (mgmt == TD_NULL) { soc_log_err("para is null!\n"); return 0; } reg.u32 = tsc_read_reg_tx(mgmt->io_base, TX_INT_TYPE); return reg.bits.tx_pkt_cnt_int; } /* Get the Tx Dsc Rd interrupt status */ td_u32 tsc_hal_tx_get_dsc_rd_int_status(const struct tsr2rcipher_mgmt *mgmt, td_u32 id) { td_u32 reg_index; td_u32 bit_offset; td_u32 reg; if (mgmt == TD_NULL) { soc_log_err("para is null!\n"); return 0; } tsr2rcipher_check_condition_return_value(id >= mgmt->ch_cnt, 0); reg_index = id / INT_FLAG_REG_NUM; bit_offset = id % INT_FLAG_REG_NUM; reg = tsc_read_reg_tx(mgmt->io_base, ISTA_TX_DSPTOR0(reg_index)); return (reg & (1U << bit_offset)); } /* Cls Tx Dsc Rd Int status */ td_void tsc_hal_tx_cls_dsc_rd_int_status(const struct tsr2rcipher_mgmt *mgmt, td_u32 id) { U_IRAW_TX reg; U_IRAW_TX reg_cls; if (mgmt == TD_NULL) { soc_log_err("para is null!\n"); return; } tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt); reg.u32 = 0; reg_cls.u32 = 0; reg.bits.iraw_tx_dsptor_done = 1; tsc_write_reg_tx(mgmt->io_base, IRAW_TX(id), reg.u32); } /* Get the Tx Pkt cnt interrupt status */ td_u32 tsc_hal_tx_get_pkt_cnt_int_status(const struct tsr2rcipher_mgmt *mgmt, td_u32 id) { td_u32 reg_index; td_u32 bit_offset; td_u32 reg; if (mgmt == TD_NULL) { soc_log_err("para is null!\n"); return 0; } tsr2rcipher_check_condition_return_value(id >= mgmt->ch_cnt, 0); reg_index = id / INT_FLAG_REG_NUM; bit_offset = id % INT_FLAG_REG_NUM; reg = tsc_read_reg_tx(mgmt->io_base, ISTA_TX_PKT_CNT0(reg_index)); return (reg & (1U << bit_offset)); } /* Cls Tx Pkt Cnt Int status */ td_void tsc_hal_tx_cls_pkt_cnt_int_status(const struct tsr2rcipher_mgmt *mgmt, td_u32 id) { U_IRAW_TX reg; U_IRAW_TX reg_cls; if (mgmt == TD_NULL) { soc_log_err("para is null!\n"); return; } tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt); reg.u32 = 0; reg_cls.u32 = 0; reg.bits.iraw_tx_pkt_cnt = 1; tsc_write_reg_rx(mgmt->io_base, IRAW_TX(id), reg.u32); tsc_com_equal(reg_cls.u32, tsc_read_reg_tx(mgmt->io_base, IRAW_TX(id))); } /* Get the Total Dsc Rd interrupt Register value */ td_void tsc_hal_tx_get_dsc_rd_total_int_value(const struct tsr2rcipher_mgmt *mgmt, td_u32 *value_array) { td_u32 i; td_u32 array_cnt; if ((mgmt == TD_NULL) || (value_array == TD_NULL)) { soc_log_err("para is null!\n"); return; } if ((td_s32)mgmt->ch_cnt <= 1) { return; } array_cnt = (mgmt->ch_cnt - 1) / INT_FLAG_REG_NUM; for (i = 0; i < array_cnt; i++) { value_array[i] = tsc_read_reg_tx(mgmt->io_base, ISTA_TX_DSPTOR0(i)); } } /* Get the Total Pkt interrupt regitster value */ td_void tsc_hal_tx_get_pkt_cnt_total_int_value(const struct tsr2rcipher_mgmt *mgmt, td_u32 *value_array) { td_u32 i; td_u32 array_cnt; if ((mgmt == TD_NULL) || (value_array == TD_NULL)) { soc_log_err("para is null!\n"); return; } if ((td_s32)mgmt->ch_cnt <= 1) { return; } array_cnt = (mgmt->ch_cnt - 1) / INT_FLAG_REG_NUM; for (i = 0; i < array_cnt; i++) { value_array[i] = tsc_read_reg_tx(mgmt->io_base, ISTA_TX_PKT_CNT0(i)); } } /* Set Top interrupt */ td_void tsc_hal_top_set_int(const struct tsr2rcipher_mgmt *mgmt, td_bool rx_int, td_bool tx_int, td_bool cipher_int) { U_TSC_IENA reg; if (mgmt == TD_NULL) { soc_log_err("para is null!\n"); return; } reg.u32 = TSC_READ_REG_TOP(mgmt->io_base, TSC_IENA); reg.bits.rx2cpu_iena = (rx_int == TD_TRUE ? 1 : 0); reg.bits.tx2cpu_iena = (tx_int == TD_TRUE ? 1 : 0); reg.bits.cipher2cpu_iena = (cipher_int == TD_TRUE ? 1 : 0); TSC_WRITE_REG_TOP(mgmt->io_base, TSC_IENA, reg.u32); tsc_com_equal(reg.u32, TSC_READ_REG_TOP(mgmt->io_base, TSC_IENA)); } /* Get Top Rx interrupt status */ td_u32 tsc_hal_top_get_rx_int_status(const struct tsr2rcipher_mgmt *mgmt) { U_TSC_ISTA reg; if (mgmt == TD_NULL) { soc_log_err("para is null!\n"); return 0; } reg.u32 = TSC_READ_REG_TOP(mgmt->io_base, TSC_ISTA); return reg.bits.rx2cpu_ista; } /* Get Top Rx Raw interrupt status */ td_u32 tsc_hal_top_get_rx_raw_int_status(const struct tsr2rcipher_mgmt *mgmt) { U_TSC_IRAW reg; if (mgmt == TD_NULL) { soc_log_err("para is null!\n"); return 0; } reg.u32 = TSC_READ_REG_TOP(mgmt->io_base, TSC_IRAW); return reg.bits.rx2cpu_iraw; } /* Cls Top Rx interrupt status */ td_void tsc_hal_top_cls_rx_int_status(const struct tsr2rcipher_mgmt *mgmt) { U_TSC_IRAW reg; U_TSC_IRAW reg_cls; if (mgmt == TD_NULL) { soc_log_err("para is null!\n"); return; } reg.u32 = 0; reg_cls.u32 = 0; reg.bits.rx2cpu_iraw = 1; TSC_WRITE_REG_TOP(mgmt->io_base, TSC_IRAW, reg.u32); } /* Get Top Tx interrupt status */ td_u32 tsc_hal_top_get_tx_int_status(const struct tsr2rcipher_mgmt *mgmt) { U_TSC_ISTA reg; if (mgmt == TD_NULL) { soc_log_err("para is null!\n"); return 0; } reg.u32 = TSC_READ_REG_TOP(mgmt->io_base, TSC_ISTA); return reg.bits.tx2cpu_ista; } /* Get Top Tx Raw interrupt status */ td_u32 tsc_hal_top_get_tx_raw_int_status(const struct tsr2rcipher_mgmt *mgmt) { U_TSC_IRAW reg; if (mgmt == TD_NULL) { soc_log_err("para is null!\n"); return 0; } reg.u32 = TSC_READ_REG_TOP(mgmt->io_base, TSC_IRAW); return reg.bits.tx2cpu_iraw; } /* Cls Top Tx interrupt status */ td_void tsc_hal_top_cls_tx_int_status(const struct tsr2rcipher_mgmt *mgmt) { U_TSC_IRAW reg; U_TSC_IRAW reg_cls; if (mgmt == TD_NULL) { soc_log_err("para is null!\n"); return; } reg.u32 = 0; reg_cls.u32 = 0; reg.bits.tx2cpu_iraw = 1; TSC_WRITE_REG_TOP(mgmt->io_base, TSC_IRAW, reg.u32); } /* Get Top Cipher interrupt status */ td_u32 tsc_hal_top_get_cipher_int_status(const struct tsr2rcipher_mgmt *mgmt) { U_TSC_ISTA reg; if (mgmt == TD_NULL) { soc_log_err("para is null!\n"); return 0; } reg.u32 = TSC_READ_REG_TOP(mgmt->io_base, TSC_ISTA); return reg.bits.cipher2cpu_ista; } /* Get Top Cipher interrupt status */ td_u32 tsc_hal_top_get_cipher_raw_int_status(const struct tsr2rcipher_mgmt *mgmt) { U_TSC_IRAW reg; if (mgmt == TD_NULL) { soc_log_err("para is null!\n"); return 0; } reg.u32 = TSC_READ_REG_TOP(mgmt->io_base, TSC_IRAW); return reg.bits.cipher2cpu_iraw; } /* Cls Top Rx interrupt status */ td_void tsc_hal_top_cls_cipher_int_status(const struct tsr2rcipher_mgmt *mgmt) { U_TSC_IRAW reg; U_TSC_IRAW reg_cls; if (mgmt == TD_NULL) { soc_log_err("para is null!\n"); return; } reg.u32 = 0; reg_cls.u32 = 0; reg.bits.cipher2cpu_iraw = 1; TSC_WRITE_REG_TOP(mgmt->io_base, TSC_IRAW, reg.u32); } td_void tsc_hal_init_hw(const struct tsr2rcipher_mgmt *mgmt) { #ifndef CONFIG_SOCT_TEE_SUPPORT tsc_tee_crg_ctrl tee_crg_ctrl; if ((mgmt == TD_NULL) || (mgmt->tee_crg_ctrl_base == TD_NULL)) { soc_log_err("para is null!\n"); return; } tee_crg_ctrl.u32 = tsc_read_reg(mgmt->tee_crg_ctrl_base, TSC_TEE_CRG_CTRL_REGS_OFFSET); tee_crg_ctrl.bits.tsc_srst_req = 1; tsc_write_reg(mgmt->tee_crg_ctrl_base, TSC_TEE_CRG_CTRL_REGS_OFFSET, tee_crg_ctrl.u32); tee_crg_ctrl.bits.tsc_cken = 1; tee_crg_ctrl.bits.tsc_srst_req = 0; tsc_write_reg(mgmt->tee_crg_ctrl_base, TSC_TEE_CRG_CTRL_REGS_OFFSET, tee_crg_ctrl.u32); #endif return; } td_void tsc_hal_de_init_hw(const struct tsr2rcipher_mgmt *mgmt) { #ifndef CONFIG_SOCT_TEE_SUPPORT tsc_tee_crg_ctrl tee_crg_ctrl; if ((mgmt == TD_NULL) || (mgmt->tee_crg_ctrl_base == TD_NULL)) { soc_log_err("para is null!\n"); return; } tee_crg_ctrl.u32 = tsc_read_reg(mgmt->tee_crg_ctrl_base, TSC_TEE_CRG_CTRL_REGS_OFFSET); tee_crg_ctrl.bits.tsc_srst_req = 1; tsc_write_reg(mgmt->tee_crg_ctrl_base, TSC_TEE_CRG_CTRL_REGS_OFFSET, tee_crg_ctrl.u32); tee_crg_ctrl.bits.tsc_cken = 0; tee_crg_ctrl.bits.tsc_srst_req = 0; tsc_write_reg(mgmt->tee_crg_ctrl_base, TSC_TEE_CRG_CTRL_REGS_OFFSET, tee_crg_ctrl.u32); #endif return; } td_void tsc_hal_en_mmu(struct tsr2rcipher_mgmt *mgmt) { U_TSC_MMU_NOSEC_EN mmu_nosec_en; td_ulong cb_ttbr = 0; td_ulong err_rd_addr = 0; td_ulong err_wr_addr = 0; td_u32 i; if (mgmt == TD_NULL) { soc_log_err("para is null!\n"); return; } if (ext_drv_sys_get_capability(EXT_SYS_CAP_TYPE_SMMU_SUPPORT) != TD_TRUE) { return; } osal_mem_get_nssmmu_pgtinfo(&cb_ttbr, &err_rd_addr, &err_wr_addr); mgmt->cb_ttbr = cb_ttbr; /* hw restrict cb_ttbr must be 16bytes align. */ WARN_ON(cb_ttbr % 16); TSC_WRITE_REG_TOP(mgmt->io_base, TSC_MMU_NOSEC_TLB, cb_ttbr >> 4); /* right shift 4 bits to get base table */ TSC_WRITE_REG_TOP(mgmt->io_base, TSC_MMU_RX_NOSEC_EADDR_L, (td_u32)(err_rd_addr & 0xFFFFFFFFU)); TSC_WRITE_REG_TOP(mgmt->io_base, TSC_MMU_TX_NOSEC_EADDR_L, (td_u32)(err_wr_addr & 0xFFFFFFFFU)); /* right shift 32 bits to get high 4 bits */ TSC_WRITE_REG_TOP(mgmt->io_base, TSC_MMU_RX_NOSEC_EADDR_H, (td_u32)((err_rd_addr >> 32) & 0xFU)); /* right shift 32 bits to get high 4 bits */ TSC_WRITE_REG_TOP(mgmt->io_base, TSC_MMU_TX_NOSEC_EADDR_H, (td_u32)((err_wr_addr >> 32) & 0xFU)); mmu_nosec_en.u32 = TSC_READ_REG_TOP(mgmt->io_base, TSC_MMU_NOSEC_EN); mmu_nosec_en.bits.sw_nosec_mmu_en = 1; TSC_WRITE_REG_TOP(mgmt->io_base, TSC_MMU_NOSEC_EN, mmu_nosec_en.u32); tsc_com_equal(mmu_nosec_en.u32, TSC_READ_REG_TOP(mgmt->io_base, TSC_MMU_NOSEC_EN)); for (i = 0; i < 8; i++) { /* the num of clear rx page table register is 8 */ TSC_WRITE_REG_TOP(mgmt->io_base, TSC_MMU_RX_CLR(i), 0xFFFFFFFF); } for (i = 0; i < 8; i++) { /* the num of clear tx page table register is 8 */ TSC_WRITE_REG_TOP(mgmt->io_base, TSC_MMU_TX_CLR(i), 0xFFFFFFFF); } } td_void tsc_hal_dis_mmu(const struct tsr2rcipher_mgmt *mgmt) { U_TSC_MMU_NOSEC_EN mmu_nosec_en; if (mgmt == TD_NULL) { soc_log_err("para is null!\n"); return; } if (ext_drv_sys_get_capability(EXT_SYS_CAP_TYPE_SMMU_SUPPORT) != TD_TRUE) { return; } mmu_nosec_en.u32 = TSC_READ_REG_TOP(mgmt->io_base, TSC_MMU_NOSEC_EN); mmu_nosec_en.bits.sw_nosec_mmu_en = 0; TSC_WRITE_REG_TOP(mgmt->io_base, TSC_MMU_NOSEC_EN, mmu_nosec_en.u32); tsc_com_equal(mmu_nosec_en.u32, TSC_READ_REG_TOP(mgmt->io_base, TSC_MMU_NOSEC_EN)); } /* Set the Mdsc Enable register */ td_void tsc_hal_mdscset_en(const struct tsr2rcipher_mgmt *mgmt, td_u32 id, td_bool ca_en, td_bool ca_chan_scr_en) { U_MDSC_EN reg; if (mgmt == TD_NULL) { soc_log_err("para is null!\n"); return; } tsr2rcipher_check_condition_return_void(id >= mgmt->ch_cnt); reg.u32 = TSC_READ_REG_MDSC(mgmt->io_base, MDSC_EN); reg.bits.ca_en = ca_en ? 1 : 0; reg.bits.ts_ctrl_dsc_change_en = ca_chan_scr_en ? 1 : 0; TSC_WRITE_REG_MDSC(mgmt->io_base, MDSC_EN, reg.u32); tsc_com_equal(reg.u32, TSC_READ_REG_MDSC(mgmt->io_base, MDSC_EN)); }