/* * Copyright (c) Hisilicon Technologies Co., Ltd. 2020-2020. All rights reserved. * Description: spi-nor and nand universal module * Author: Hisilicon * Create: 2020-10-15 */ #ifndef NAND_H #define NAND_H /******************************************************************************/ #include #include "td_type.h" #include "uapi_flash.h" #define MTD_ABSENT 0 #define MTD_RAM 1 #define MTD_ROM 2 #define MTD_SPIFLASH 3 #define MTD_NANDFLASH 4 /* SLC NAND */ #define MTD_DATAFLASH 6 #define MTD_UBIVOLUME 7 #define MTD_MLCNANDFLASH 8 /* MLC NAND (including TLC) */ #define DEV_MTDBASE "/dev/mtd" #define MAX_DEV_NAME_LEN 12 #define MAX_PART_NAME_LEN 32 #define PROC_MTD_FILE "/proc/mtd" #define STRTOULL_BASE_DEC 10 #define STRTOULL_BASE_HEX 16 /*****************************************************************************/ struct mtd_info_user { uint8_t type; uint32_t flags; uint32_t size; uint32_t erasesize; uint32_t writesize; uint32_t oobsize; uint32_t ecctype; uint32_t eccsize; }; #define MEMGETINFO _IOR('M', 1, struct mtd_info_user) struct erase_info_user64 { uint64_t start; uint64_t length; }; #define MEMERASE64 _IOW('M', 20, struct erase_info_user64) struct mtd_oob_buf { uint32_t start; uint32_t length; td_u8 *ptr; }; #define MEMREADOOB _IOWR('M', 4, struct mtd_oob_buf) /** * struct mtd_write_req - data structure for requesting a write operation * * @start: start address * @len: length of data buffer * @ooblen: length of OOB buffer * @usr_data: user-provided data buffer * @usr_oob: user-provided OOB buffer * @mode: MTD mode (see "MTD operation modes") * @padding: reserved, must be set to 0 * * This structure supports ioctl(MEMWRITE) operations, allowing data and/or OOB * writes in various modes. To write to OOB-only, set @usr_data == NULL, and to * write data-only, set @usr_oob == NULL. However, setting both @usr_data and * @usr_oob to NULL is not allowed. */ struct mtd_write_req { uint64_t start; uint64_t len; uint64_t ooblen; uint64_t usr_data; uint64_t usr_oob; uint8_t mode; uint8_t padding[7]; /* 7 - buffer size */ }; #define MEMWRITE _IOWR('M', 24, struct mtd_write_req) #define MEMGETBADBLOCK _IOW('M', 11, long long) #define MEMSETBADBLOCK _IOW('M', 12, long long) #define MEMFORCEERASEBLOCK _IOW('M', 128, long long) /*****************************************************************************/ struct mtd_partition { uint64_t start; uint64_t end; int readonly; uapi_flash_access_perm perm; char mtddev[MAX_DEV_NAME_LEN]; char partname[MAX_PART_NAME_LEN]; td_s32 fd; }; struct nand_raw_ctrl { td_s32 num_partition; uint64_t size; uint32_t pagesize; uint32_t blocksize; uint32_t oobsize; uint32_t oobused; uint32_t pageshift; uint32_t blockshift; uint32_t pagemask; uint32_t blockmask; struct mtd_partition partition[1]; }; #define dbg_out(fmt, arg...) td_char *int_to_size(td_u64 size); td_s32 get_max_partition(td_void); td_s32 offshift(td_ulong n); td_s32 flash_partition_info_init(td_void); uapi_flash_partinfo *get_flash_partition_info(uapi_flash_type flash_type, const td_char *devname, td_u32 dev_len); /******************************************************************************/ #endif /* NAND_H */